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Labtools can be used if pre-built images for FPGA are available, for debugging also the debug netlist file is needed.

 

Example Debug Session

 

TE0715

TE0715-xx-15 Micromodule with "VIO only" labtools pre-built design. This design does not depend on the PS subsystem being initialized by the Zynq Bootrom.

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XADC can also be monitored to check the temperature and voltage sensor values.

TE0720