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Clock measurements: 125MHz is Clock from Ethernet PHY, CFGCLK is FPGA internal configuration clock (nominal frequency 66MHz). TE0720 has no fixed PL clock sources, so the labtools design uses free running clock for all VIO's and PS supplied clock FCLK0 or FCLK3 as reference clock (it can be selected by changing PLL_REFSEL to 1 for FCLK0).
If the PS subsystem has executed FSBL (or it failed) then there are no clocks from PS, also the FCLK_RESET read as 0, this is indication that PS is not running at all.
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