Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Perihery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic TE0817 is an industrial grade MPSoC SOM SoM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0817-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC
- Device: ZU4 / ZU5 / ZU7 ¹⁾
- Engine: CG / EG / EV ¹⁾
- Speedgrade: -1 / -2 / -3 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: FBVB900
RAM/Storage
- 4 GByte DDR4 SDRAM ²⁾
- 2 x 64 MByte Serial Flash ³⁾
- EEPROM with MAC address
On Board
- Oscillator
Interface
- 4 x B2B Connector (ADM6)
  - up to 204 PL IO
    - HP: 156
    - HD: 48
  - up to 65 PS MIO
  - 4 GTR
  - 16 GTH
  - I2C, JTAG
Power
- 3.3 V power Power supply via B2B Connector needed ⁴⁾.
Dimension
- 76 mm x 52 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.⁴⁾ Dependant on the assembly option a higher input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0817 block diagram

Scroll Ignore

draw.io Diagram

border	true

diagramName	TE0817_OV_BD
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	641642
revision	45

Scroll Only

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0817 main components

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	721
revision	7

Scroll Only

SoC, U1
DDR4, U2, U3, U9, U12
Quad SPI Flash, U7, U17
Connector, J1, J2, J3, J4
EEPROM, U11
Clock Generator, U5
Oscillator, U25, U32

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
DDR4 SDRAM	not programmed
Quad SPI Flash	not programmed
EEPROM	not programmed besides factory programmed MAC address
Programmable Clock Generator	not programmed

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector Type	Designator	Interface	IO CNT ¹⁾
B2B	JM1J1	MGT PL	12 x MGT (RX/TX)
B2B	JM1J1	HP	52 SE / 24 DIFF
B2B	JM2J2	MGT PS	2 x MGT CLK
B2B	JM2J2	CLK	DIFF CLK
B2B	JM2J2	MGT PL	4 x MGT (RX/TX)
B2B	JM2J2	MGT PS	4 x MGT (RX/TX)
B2B	JM2J2	CFG	JTAG
B2B	JM2J2	CFG	MODE
B2B	JM3J3	HD	48 SE / 24 DIFF
B2B	JM3J3	MGT PL	3 x MGT CLK
B2B	JM3J3	CLK	DIFF CLK
B2B	JM3J3	MIO	65 GPIO
B2B	JM4J4	HP	104 SE / 48 DIFF

¹⁾ IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

PointNotes1TP12PLVCCINTTP15

Test	Point ¹⁾	Signal
TP1	PLL_SCL	pulled-up to SI_PLL_1V8
TP2	PLL_SDA	pulled-up to SI_PLL_1V8
TP3	DDR4-TEN	pulled-down to GND
TP4	VTT
TP5	GND
TP6	TCK
TP7	TDI
TP8	TDO
TP9	TMS
TP10	LP_	0V85
TP11	FP_0V85
TP12	PL_VCCINT
TP13	PS_PLL
TP14	PS_GT_1V0
TP15	FP_0V85
TP16	DDR_2V5
TP17	DCDC_2V0
TP18	DDR_PLL
TP19	PS_GT_1V0
TP20	PL_VCU
TP21	PS_AUX
TP22	PS_AVCC
TP23	VTT
TP24	AUX_R
TP25	AVTT_R
TP26	AVCC_R
TP27	PS_PLL
TP28	PS_AVTT
TP29	PS_AUX
TP30	PS_AVCC
TP31	LP_0V85
TP32	GND

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:


TP33	PS_AVTT
TP34	DDR_PLL
TP35	DDR_2V5
TP36	VREFA
TP37	VREFA
TP38	3.3VIN
TP39	LP_DCDC
TP40	PL_VCCINT
TP41	DCDCIN
TP42	DCDC_2V0
TP43	PL_DCIN
TP44	PL_GT_1V45
TP45	PL_GT_1V45
TP46	GT_DCDC
TP47	PL_GT_1V15
TP48	PL_GT_1V15
TP49	PLL_3V3
TP50	AUX_R
TP51	PSBATT
TP52	AVCC_R
TP53	AVTT_R
TP54	VCCO_47
TP55	PL_VCU
TP56	VCCO_48
TP57	1V8_REFIN
TP58	1V8_REFIN
TP59	VCCO_64
TP60	1V25_REF
TP61	1V25_REF
TP62	VCCO_65
TP63	VCCO_66
TP64	PLL_VDDA
TP65	PLL_VDDA
TP66	PLL_VDD
TP67	PLL_VDD
TP68	PS_1V8
TP69	PL_1V8
TP70	SI_PLL_1V8
TP71	SI_PLL_1V8
TP72	DDR4_1V2

¹⁾ Test points depend on revision: Not all testpoints are available for all revisions.

²⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait

Chip/InterfaceDesignatorConnected ToNotesETH PHYU10

B2B connector J1
SoC MIO

Gigabit ETH PHY Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueChip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2, U3, U9, U12SoC - PS

Quad SPI Flash

U7, U17SoC - PSBooting.

EEPROM

U11B2B - J2

Clock Generator

U5SoC, B2B

Oscillator

U25Clock Generator25 MHz

Oscillator

U32SoC33.333333 MHz

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

AnchorConfiguration and System Control SignalsConfiguration and System Control Signals

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id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin

Signal Name

Direction¹⁾

Description

JM1.A45

POR_OVERRIDE

IN

Override power-on reset delay ²⁾.

JM2.A30

PG_PLL_1V8

OUT

SI_PLL_1V8 power rail powered-up.

JM2.A31

ERR_OUT

OUT

PS error indication ²⁾.

JM2.A34

ERR_STATUS

OUT

PS error status ²⁾.

JM2.A35

LP_GOOD

OUT

Low-power domain powered-up. Pulled up to 3.3VIN

JM2.A36

PLL_SCL

IN

I2C clock

JM2.A37

PLL_SDA

IN/OUT

I2C data

JM2.A40

PG_VCU

OUT

VCU power rail powered-up.

JM2.A41

EN_PSGT

IN

Enable GTR transceiver power-up.

JM2.A44 / JM2.A45 /
JM2.A46 / JM2.A47

TCK / TDI / TDO / TMS

Signal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

JM2.B29

PG_PSGT

OUT

GTR transceivers powered-up.

JM2.B30

PROG_B

IN/OUT

Power-on reset ²⁾. Pulled-up to PS_1V8.

JM2.B33

SRST_B

IN

System reset ²⁾. Pulled-up to PS_1V8.

JM2.B34

INIT_B

IN/OUT

Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.

JM2.B37

PG_PL

OUT

Programmable logic powered-up.

JM2.B38

EN_FPD

IN

Enable full-power domain power-up.

JM2.B41

PG_FPD

OUT

Full-power domain powered-up.

JM2.B42

EN_LPD

IN

Enable low-power domain power-up.

JM2.B45

PG_DDR

OUT

DDR power supply powered-up.

JM2.B46

DONE

OUT

PS done signal ²⁾. Pulled-up to PS_1V8.

JM2.B47

EN_DDR

IN

Enable DDR power-up.

JM2.C30

EN_GT_L

IN

Not connected.

JM2.C31

MR

IN

Manual reset.

JM2.C32

PLL_SEL0

IN

PLL clock selection.

JM2.C33

PLL_RST

IN

PLL reset.

JM2.C35

EN_PL

IN

Enable programable logic power-up.

JM2.C36

EN_GT_R

IN

Enable GTH transceiver power-up.

JM2.C37

PLL_FDEC

IN

PLL Frequency decrementation.

JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47

MODE3..0

IN

Boot mode selection ²⁾:

JTAG
QUAD-SPI (32 Bit)
SD1 (2.0)
eMMC (1.8 V)
SD1 LS (3.0)

Supported Modes depends also on used Carrier.

JM2.D29

EN_PLL_PWR

IN

Enable PLL power supply.

JM2.D30

PLL_FINC

IN

PLL Frequency incrementation.

JM2.D31

PLL_LOLn

OUT

Loss of lock status.

JM2.D32

PLL_SEL1

IN

PLL clock selection.

JM2.D33

PG_GT_R

OUT

GTH Transceivers powered-up.

JM2.D37

PSBATT

IN

PS RTC Battery supply voltage ^{2) 3)}.

JM2.D38

PUDC_B

IN

Configuration pull-ups setting ²⁾. Pulled-up to PL_1V8.

JM2.D45 / JM2.D46

DX_P / DX_N

-

SoC temperatur sensing diode pins ²⁾.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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id	Comments

List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name/ Schematic NameConnector.PinDirection¹⁾Notes

Chip/Interface	Designator	Connected To	Notes
DDR4 SDRAM	U2, U3, U9, U12	SoC - PS
Quad SPI Flash	U7, U17	SoC - PS	Booting.
EEPROM	U11	B2B - J2
Clock Generator	U5	SoC, B2B
Oscillator	U25	Clock Generator	25 MHz
Oscillator	U32	SoC	33.333333 MHz

Page properties

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

Anchor

	Configuration and System Control Signals
	Configuration and System Control Signals

Page properties

hidden	true
id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin	Signal Name	Direction¹⁾	Description
JM1.A45	POR_OVERRIDE	IN	Override power-on reset delay ²⁾.
JM2.A30	PG_PLL_1V8	OUT	SI_PLL_1V8 power rail powered-up.
JM2.A31	ERR_OUT	OUT	PS error indication ²⁾.
JM2.A34	ERR_STATUS	OUT	PS error status ²⁾.
JM2.A35	LP_GOOD	OUT	Low-power domain powered-up. Pulled up to 3.3VIN
JM2.A36	PLL_SCL	IN	I2C clock
JM2.A37	PLL_SDA	IN/OUT	I2C data
JM2.A40	PG_VCU	OUT	VCU power rail powered-up.
JM2.A41	EN_PSGT	IN	Enable GTR transceiver power-up.
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47	TCK / TDI / TDO / TMS	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8
JM2.B29	PG_PSGT	OUT	GTR transceivers powered-up.
JM2.B30	PROG_B	IN/OUT	Power-on reset ²⁾. Pulled-up to PS_1V8.
JM2.B33	SRST_B	IN	System reset ²⁾. Pulled-up to PS_1V8.
JM2.B34	INIT_B	IN/OUT	Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.
JM2.B37	PG_PL	OUT	Programmable logic powered-up.
JM2.B38	EN_FPD	IN	Enable full-power domain power-up.
JM2.B41	PG_FPD	OUT	Full-power domain powered-up.
JM2.B42	EN_LPD	IN	Enable low-power domain power-up.
JM2.B45	PG_DDR	OUT	DDR power supply powered-up.
JM2.B46	DONE	OUT	PS done signal ²⁾. Pulled-up to PS_1V8.
JM2.B47	EN_DDR	IN	Enable DDR power-up.
JM2.C30	EN_GT_L	IN	Not connected.
JM2.C31	MR	IN	Manual reset.
JM2.C32	PLL_SEL0	IN	PLL clock selection.
JM2.C33	PLL_RST	IN	PLL reset.
JM2.C35	EN_PL	IN	Enable programable logic power-up.
JM2.C36	EN_GT_R	IN	Enable GTH transceiver power-up.
JM2.C37	PLL_FDEC	IN	PLL Frequency decrementation.
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47	MODE3..0	IN	Boot mode selection ²⁾: JTAG QUAD-SPI (32 Bit) SD1 (2.0) eMMC (1.8 V) SD1 LS (3.0) Supported Modes depends also on used Carrier.
JM2.D29	EN_PLL_PWR	IN	Enable PLL power supply.
JM2.D30	PLL_FINC	IN	PLL Frequency incrementation.
JM2.D31	PLL_LOLn	OUT	Loss of lock status.
JM2.D32	PLL_SEL1	IN	PLL clock selection.
JM2.D33	PG_GT_R	OUT	GTH Transceivers powered-up.
JM2.D37	PSBATT	IN	PS RTC Battery supply voltage ^{2) 3)}.
JM2.D38	PUDC_B	IN	Configuration pull-ups setting ²⁾. Pulled-up to PL_1V8.
JM2.D45 / JM2.D46	DX_P / DX_N	-	SoC temperatur sensing diode pins ²⁾.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Power and Power-On Sequence

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id	Comments

Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

Page properties

hidden	true
id	Comments

List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾
VCCO_66	JM1.A32 / JM1.A33	IN
VREF_66	JM1.A41	IN
3.3VIN	JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56	IN
PL_1V8	JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34	OUT
PL_DCIN	JM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60	IN
LP_DCDC	JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52	IN
DCDCIN	JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 /	IN
PS_BATT	JM2.D37	IN
DDR_1V2	JM2.D47	OUT
PS_1V8	JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56	OUT
PLL_3V3	JM3.A55	IN
GT_DCDC	JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 /	IN
VCCO_48	JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9	IN
VCCO_47	JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21	IN
VCCO_64	JM4.B21 / JM4.B39	IN
VREF_64	JM4.B30	IN
VCCO_65	JM4.C21 / JM4.C39	IN
VREF_65	JM4.C30	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

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Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
1	3.3VIN	3.3 V (± 5 %)	-	Management power supply.	Management module power supply. 0.5 A recommended.
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.):
1 ¹⁾	GT_DCDC	3.3 V (± 3 %) ²⁾		GTH transceiver power supply.	Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
1 ¹⁾	EN_PLL_PWR	-	PD ³⁾, GND	PLL power enable.
1 ¹⁾	PG_PLL_1V8

VCCO_66JM1.A32 / JM1.A33INVREF_66JM1.A41IN3.3VINJM1.A54 / JM1.A55 / JM1.B55 / JM1.B56IN

PL_1V8

JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34OUTPL_DCINJM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60INLP_DCDCJM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52INDCDCINJM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / INPS_BATTJM2.D37INDDR_1V2JM2.D47OUTPS_1V8JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56OUTPLL_3V3JM3.A55INGT_DCDCJM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 /INVCCO_48JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9INVCCO_47JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21INVCCO_64JM4.B21 / JM4.B39INVREF_64JM4.B30INVCCO_65JM4.C21 / JM4.C39INVREF_65JM4.C30IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

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LP_GOODLow-power domain 4PG_VCUVCU GTH / GTY Transceiver GTH / GTY transceiver 3GTDCDCGTH transceiver GTH transceiver 5 GT_R3GTH / GTY transceiver GT_RGTH / GTY transceiver

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
1	3.3VIN	3.3 V (± 5 %)	-	Management power supply.	Management module power supply. 0.5 A recommended.
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.):
1 ¹⁾	GT_DCDC	3.3 V (± 5 %) ²⁾	GTH transceiver power supply.	Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.	1 ¹⁾	EN_PLL_PWR	-	PD ³⁾, GND	PLL power enable.	1 ¹⁾	PG_PLL_1V8	-	PU ³⁾, 3.3 V	PLL power good status.	2	Processing System (PS):	Procedure for PS starting.	2.1	Low-power domain:	Bring-up for low-power domain PS.
2.1.1	LP_DCDC	3.3 V (± 5 %) ²⁾	-	Low-power domain power supply.	Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2	EN_LPD	-	PU ³⁾, 3.3 V	Low-power domain power enable.	2.1.3		-	PU ³⁾, 3.3 V	PLL power good status.	Module power-on sequencing for low-power domain finished.
2.2	Processing System (PS):			Procedure for PS starting.
2.1	LowFull-power domain:			Bring-up for fulllow-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.21.1	DCDCINLP_DCDC	3.3 V (± 5 3 %) ²⁾	-	LowFull-power domainand GTR transceiver domain power supply.	Main module power supply for fulllow-power domain. 5. 7 5 A recommended. Power consumption depends mainly on design and cooling solution.
2.21.2	EN_FPDLPD	-	PU ³⁾, 3.3 V	Low-Full-power domain power enable.
2.21.3	PGLP_FPDGOOD	-	PU ³⁾, 3.3 V	FullLow-power domain power good status.	Module power-on sequencing for fulllow-power domain finished.
2.2.4	EN_DDR	3.3 V	-	DDR memory power enable.	2.2.5	PG_DDR	PU ³⁾, 3.3 V	DDR memory power good status.	Module power-on sequencing for DDR memory finished.
2.3	GTR Transceiver			Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
	Full-power domain:			Bring-up for full-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.2.1	DCDCIN	3.3 V (± 5 %) ²⁾		Full-power domainand GTR transceiver power supply.	Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2	EN_FPD	3.3 V	-	Full-power domain power enable.
2.2.3	PG_FPD	2.3.1	EN_PSGT	3.3 V	-	GTR transceiver power enable.	2.3.2	PG_PSGT	-	PU ³⁾, 3.3 V	GTR transceiver Full-power domain power good status.	Module power-on sequencing for GTR transceiver full-power domain finished.
2	Programmable Logic (PL)			Procedure for PL starting.	PS and PL can be started independently.	2.14	PLEN_DCINDDR	3.3 V (± 5 %) ²⁾ ⁴⁾	-	Programmable logic power supply.	Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.		-	DDR memory power enable.
2.2.5	PG_DDR		2.2	EN_PL	-	PU ³⁾, 3.3 V	Programmable logic power enable.	2.3	PG_PL	-	PU ³⁾, 3.3 V	Programmable logic DDR memory power good status.	Module power-on sequencing for programmable logic DDR memory finished. Periphery and variable bank voltages can be enabled on carrier.
2.	3	GTR Transceiver			Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1	EN_PSGT	3.3 V	-	GTR transceiver power enable.
2.3.2	PG_PSGT	VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66	⁵⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.	2.5		-	PU ³⁾, 3.3 V	GTR transceiver power good status.	3	Module power-on sequencing for GTR transceiver finished.
2	Programmable Logic (PL)			Procedure for	PL starting.	PL transceiver usage needs powered PL and low-power PS domain.	PS and PL can be started independently.
2	.1	PL_	DCIN	3.3 V (± 5 %) ²⁾ ⁴⁾	-	Programmable logic power supply.	Main module power supply for	programmable logic.	12 A recommended. Power consumption depends mainly on design and cooling solution.3
2.2	EN_	PL	-	PU ³⁾, 3	.3 V	-	Programmable logic power enable.3
2.3	PG_	PL	-	PU ³⁾, 3.3 V	Programmable logic power good status.

¹⁾ (optional)

²⁾ Dependent on the assembly option a higher input voltage may be possible.

³⁾ (on module)

⁴⁾ This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

⁵⁾ See DS925 for additional information.

Board to Board Connectors

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Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4	VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66	⁵⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.
2.5	PG_VCU	-	PU ³⁾, 3.3 V	VCU power good status.
3	GTH / GTY Transceiver			Procedure for GTH / GTY transceiver starting.	PL transceiver usage needs powered PL and low-power PS domain.
3.1	GT_DCDC	3.3 V (± 3 %) ²⁾	-	GTH transceiver power supply.	Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.2	EN_GT_R	3.3 V	-	GTH / GTY transceiver power enable.
3.3	PG_GT_R	-	PU ³⁾, 3.3 V	GTH / GTY transceiver power good status.

¹⁾ (optional)

²⁾ Dependent on the assembly option a higher input voltage may be possible.

³⁾ (on module)

⁴⁾ This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

⁵⁾ See DS925 for additional information.

Board to Board Connectors

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use "include page" macro and link to the general B2B connector page of the module series,
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Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors
	5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
LP_DCDC	Micromodule Power	-0.300	6.0	V
DCDCIN	Micromodule Power	-0.300	7.0	V
GT_DCDC	Micromodule Power	-0.300	6.0	V

use "include page" macro and link to the general B2B connector page of the module series,

For example: 6 x 6 SoM LSHM B2B Connectors
Include Page6 x 6 SoM LSHM B2B Connectors6 x 6 SoM LSHM B2B Connectors Include Page5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

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Power Rail Name/ Schematic Name	Description	Min	Max	Unit
LP_DCDC	Micromodule Power	-0.300	6.0	V
DCDCIN	Micromodule Power	-0.300	7.0	V
GT_DCDC	Micromodule Power	-0.300	6.0	V
PL_DCIN ¹⁾	Micromodule Power	-0.300	47.0	V
3.3VIN	Micromodule Power	-0.300	3.600	V
PLL_3V3	PLL power supply	-0.500	3.8	V
PS_BATT	RTC / BBRAM	-0.500	2.000	V
VCCO_47	HD IO Bank power supply	-0.500	3.400	V
VCCO_48	HD IO Bank power supply	-0.500	3.400	V
VCCO_64	HP IO Bank power supply	-0.500	2.000	V
VCCO_65	HP IO Bank power supply	-0.500	2.000	V
VCCO_66	HP IO Bank power supply	-0.500	2.000	V
VREF_64	Bank input reference voltage	-0.500	2.000	V
VREF_65	Bank input reference voltage	-0.500	2.000	V
VREF_66	Bank input reference voltage	-0.500	2.000	V

¹⁾ This value depends highly on For REV01 use max. 4 V instead which depends highly on DCDC U4. Higher values are possible with different DCDCs. For more information consult schematic and according datasheets.

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be different depending on assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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Parameter	Min	Max	Units	Reference Document
LP_DCDC ¹⁾	3.135201	3.465399	V
DCDCIN ¹⁾	3.135	3.465	V
GT_DCDC ¹⁾	3.135201	3.465399	V
PL_DCIN ¹⁾ ²⁾	3.135	3.465	V
3.3VIN	3.135	3.465	V
PLL_3V3	3.135	3.465	V
PS_BATT	1.2	1.5	V	See FPGA datasheet.
VCCO_47	1.164	3.399	V	See FPGA datasheet.
VCCO_48	1.164	3.399	V	See FPGA datasheet.
VCCO_64	0.97	1.854	V	See FPGA datasheet.
VCCO_65	0.97	1.854	V	See FPGA datasheet.
VCCO_66	0.97	1.854	V	See FPGA datasheet.
VREF_64	0.6	1.2	V	See FPGA datasheet.
VREF_65	0.6	1.2	V	See FPGA datasheet.
VREF_66	0.6	1.2	V	See FPGA datasheet.

¹⁾ Dependent on the assembly option a higher input voltage may be possible.

²⁾ This value depends highly on REV01 DCDC U4. Higher values may possible with different DCDCs or different revision. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.

PCB thickness: 1.74 mm (± 10 %) (???).

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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revision	23

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Currently Offered Variants

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Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0813

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0813

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Trenz shop TE0817 overview page
English page	German page

Revision History

Hardware Revision History

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Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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Date	Revision	Changes	Documentation Link
2024-04	REV02	Changed DCDC (U13) from EN6347QI to MPM3860GQW-Z and apdated according circuit. Connected DDR4-TEN signals together for U2A, U3A, U9A, and U12A and pulled them low via 499 Ohm resistor R127. Added testpoint TP3 for signal DDR4-TEN. Changed voltage rail from 1.35 V to 1.45 V via adaption voltage divider resistor R30 and changed voltage rail name PL_GT_1V35 to PL_GT_1V45. Changed voltage rail from 1.05 V to 1.15 V via adaption voltage divider resistors R33 and R35 and changed voltage rail name PL_GT_1V05 to PL_GT_1V15. Added diode D2 between U41 pin 3 net MR and voltage rail 3.3VIN. Added capacitors C202 ... C205 for VTT voltage rail VTT. Added resistors R124 (default: not fitted) and R125 to supply U4 VCC either from PL_DCIN or from 3.3VIN. Changed resistor R76 from 4.22 kOhm to 9.09 kOhm to set current limit to nearly 14.3 A for U4. Added remote sense option (default: not fitted): R126 for U30. R128 for U29. R129 for U31. Added decoupling capacitors: C208 for U4. C211, C212, and C213 for U6. C216 for U10. C214 for U26. C215 for U27. C210 for U34. C196 for U39. C197 for U40. C198 for U42. C199 for U41. C200 for U44. C201, C206, and C207 for U1N. Added pull-up resistors for HOLD (R130) and WP (R131) signals for Flash U7A. Added pull-up resistors for HOLD (R132) and WP (R133) signals for Flash U17A. Changed 100 nF capacitors ( C37, C95, C96, C130, and C131) from 6.3 V, X5R, 10 %, 0201 to 50 V, X7R, 0402. Changed 10 nF capacitor ( C112) from 16 V, 0402 to 10 V, 0201. Changed capacitor (C76, C77, C134, C195) from 1 µF, 16 V to 2.2 µF, 10 V. Changed capacitor (C129, C140, C141, C142, C143, C144, C145, C146, C147, C148, C153) from 10 µF, 16 V to 22 µF, 10 V. Changed 22 uF capacitor (C70, C73, C74, C75) from 0805 to 0603. Changed 22 uF capacitor ( C78, C80, C81, C82, C83, C84, C85, C86, C87, C110, C152, C154, C178) from 6.3 V to 10 V. Changed 100 Ohm resistors (R7, R10) from 0201, 0.05 W to 0402, 0.063 W. Changed resistor R77 from 12 kOhm to 10 kOhm. Changed resistors R41 and R58 from 2 kOhm to 2.49 kOhm. Added testpoints TP4, TP10, TP11, TP13, TP14, TP19, TP21, TP22, TP33 ... TP72. Added UKCA logo. Updated from library. Changed signal trace length. Updated documentation.	REV02

Date

Revision

Changes


-	REV01	First Production Release	REV01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Date

Revision

Contributor

Description

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Updated to board REV02.

2023-03-02

v.17

Martin Rohrmüller

Corrected max possible DDR4 assembly option

2023-01-16

v.14

ED

Fixed issue in absolute maximum ratings

2022-11-08

v.13

ED

Initial Document

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 17

New Version 18

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

On-board Peripherals

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Recommended Power up Sequencing

Board to Board Connectors

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)

Absolute Maximum Ratings ^*)