Page History
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- XMOD header, JB1
- 14-pin header placeholder for connector, J3
- Xilinx Artix-7 FPGA, U1
- 1.8V, 256 MBit (32 MByte) quad SPI serial flash memory, U7
- Red LED (SYSLED), D2
- Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory, U4 (optional)
- Low-power programmable oscillator @25.000000 MHz, U3
- Low VIN high-efficiency step-down converter (1.5A max.), U5
- Low VIN high-efficiency step-down converter (1.5A max.), U6 (optional)
- 50-pin header placeholder for breadboard connector, J1J2
- 50-pin header placeholder for breadboard connector, J2J1
- Ultra-low supply-current voltage monitor with optional watchdog, U8
- 128KBit I2C CMOS serial EEPROM, U2
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TE0725LP needs one single power supply with nominal of 3.3V at the variant TE0725-01-100-2C or 1.8V at the variants TE0725LP-01-100-2D and TE0725LP-01-100-2D2L. Following diagram shows the dependencies of the power supply:
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Bank | Bank I/O Voltage VCCO | Voltage Range |
|---|---|---|
| 0 (config) | 1.8V | fixed |
| 14 (HR) | 1.8V | fixed |
| 15 (HR) | 1.8V | fixed |
| 34 (HR) | VCCIO34 | 1.2V ... 3.3V |
| 35 (HR) | VCCIO34VCCIO35 | 1.2V ... 3.3V |
Table 14: Board bank voltages
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| Date | Revision | Contributors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| v.45 | Ali Naseri, Jan Kumann |
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Table 16: Document change history
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