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Board to Board (B2B) I/Os

Overview of the I/O signals signal banks connected to the FPGAs I/O banks and B2B connectorB2B connectors:

Table 2:   Voltage ranges and pin-outs of available logic banks of the FPGAAvailable I/O signal banks connected to the B2B connectors.

Please use Master Pin-out Table table as primary reference for the pin mapping information.

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Figure 5: System Controller CPLD block diagram.

Power and Power-On Sequence

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For highest efficiency of on board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS182 ( for Kintex7) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0741 module.

The FPGA 1.0V supply is derived from two regulators operating in a parallel allowing higher load currents. To start the power-on sequence, pin EN1 (JM1-28, enable 1.0V voltage regulators) is by default high. By driving EN1 pin low on base-board the power-on sequence will not start until the EN1 pin is released to high.

A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stable. Than this power supply will be available on the B2B connector pins.

The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are detailed below.

• Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
• Apply 3.3V to pins VIN and 3.3VIN on the board connectors.

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Figure 6: Connections between the on-board DC-DC and LDO regulators-28, enable 1.0V voltage regulators) is by default high. By driving EN1 pin low on base-board the power-on sequence will not start until the EN1 pin is released to high.

Power Rails

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• Module size: 50 mm × 40 mm
• Mating height with standard connectors: 8mm
• PCB thickness: 1.6mm

Figure 76: Physical dimensions of the TE0741 module. All dimensions are shown in millimeters.

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Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 7: TE0741 PCB revision number.

Document Change History

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