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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


20220125102022-01-1492021-06-2882021-06-0172021-05-046 zynq_ from zynq_fsbl2021042852021-04-274Fix problem with pdf
DateVersionChangesAuthor
2023-12-143.1.
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma17
  • updated according to Vivado 2023.2
ma
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.
  • added boot process for Microblaze
  • minor typos, formatting
ma14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.
  • carrier reference note
jh13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed
  • content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf
ma3.1
  • export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100
Page properties
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
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Notes :

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Page properties
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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20212023.2
  • QSPI
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)

Revision History

Page properties
hiddentrue
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Notes :

  • add every update file on the download
  • add design changes on description
Expand
titleExpand List
scroll-
tablelayout
title
anchorTable_DRH
title-alignmentcenter
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Scroll Title
anchorTable_DRH
title-alignmentcenter
titleDesign Revision History
DateVivadoProject BuiltAuthorsDescription
2022
2024-03-
16
13
2021
2023.2TE0808-test_board-vivado_
2021
2023.2-build_
11
4_
20220316091917
20240313130413.zip
TE0808-test_board_noprebuilt-vivado_
2021
2023.2-build_
11
4_
20220316091917
20240313130413.zipManuela Strücker
2021
  • 2023.2 release
  • update board files
    		• 2021-05-12
    • new assembly variants
    2023-06-012022
    2020
    .2TE0808-test_board-vivado_
    2020
    2022.2-build_
    5
    1_
    20210512133121
    20230601101432.zip
    TE0808-test_board_noprebuilt-vivado_
    2020
    2022.2-build_
    5
    1_
    20210512133137
    20230601101432.zip
    John Hartfiel
    • update board files
    2021-02-05
    Manuela Strücker
    • 2022.2 release
    • new assembly variants
    2023-04-132021.2.1
    2020.2
    TE0808-test_board-vivado_
    2020
    2021.2-build_
    0
    20_
    20210204141911
    20230413090245.zip
    TE0808-test_board_noprebuilt-vivado_
    2020
    2021.2-build_
    1
    20_
    20210204142855
    20230413090245.zip
    John Hartfiel
    • 2020.2 update
    Manuela Strücker
    • new assembly variants
    2022
    2020
    -09-29
    2019
    2021.2.1TE0808-test_board
    _noprebuilt
    -vivado_
    2019
    2021.2-build_
    15
    17_
    20200929070740
    20220928203325.zip
    TE0808-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    15_20200929070725John Hartfiel
    • bugfix 8GB board parts
    17_20220928203325.zipManuela Strücker
    • script update
    • new assembly variants
    2022
    2020
    -09-
    22
    12
    2019
    2021.2.1TE0808-test_board
    _noprebuilt
    -vivado_
    2019
    2021.2-build_
    14
    15_
    20200922073159
    20220912090608.zip
    TE0808-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    14
    15_
    20200922073144
    20220912090608.zip
    John Hartfiel
    • new assembly variants
    Manuela Strücker
    • update board part files compatible to Vivado 2021.2.1
    2022
    2020
    -03-
    25
    21
    2019
    2021.2TE0808-test_board
    _noprebuilt
    -vivado_
    2019
    2021.2-build_
    8
    11_
    20200325083246
    20220321063547.zip
    TE0808-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    8
    11_
    20200325083204
    20220321063547.zipJohn Hartfiel
    • script update
    2020-01-22
    • replace Starterkit FSBL with default one
    2022-03-162021
    2019
    .2TE0808-test_board
    _noprebuilt
    -vivado_
    2019
    2021.2-build_
    3
    11_
    20200122142231
    20220316091917.zip
    TE0808-test_board_noprebuilt-vivado_
    2019
    2021.2-build_
    3
    11_
    20200122142208
    20220316091917.zip
    John Hartfiel
    Manuela Strücker
    2019
    • 2021.2 release
    • update
  • Vitis support
    • 2019-08-09
    • board files
    2021-05-122020.2
    2018.3
    TE0808-test_board
    _noprebuilt
    -vivado_
    2018
    2020.
    3
    2-build_
    07
    5_
    20190809131546
    20210512133121.zip
    TE0808-test_board_noprebuilt-vivado_
    2018
    2020.
    3
    2-build_
    07
    5_
    20190809131522
    20210512133137.zipJohn Hartfiel
    • new assembly variants
    • update board files
    2021-02
    2019
    -05
    -06
    2018
    2020.
    3
    2TE0808-test_board
    _noprebuilt
    -vivado_
    2018
    2020.
    3
    2-build_
    05
    0_
    20190507124141
    20210204141911.zip
    TE0808-test_board_noprebuilt-vivado_
    2018
    2020.
    3
    2-build_
    05
    1_
    20190507124130
    20210204142855.zipJohn Hartfiel
    • custom FSBL
    2018-07-11
    • 2020.2 update
    2020-09-292019
    2018
    .2TE0808-test_board_noprebuilt-vivado_
    2018
    2019.2-build_
    02
    15_
    20180711143743
    20200929070740.zip
    TE0808-test_board-vivado_
    2018
    2019.2-build_
    02
    15_
    20180711143702.zip
    20200929070725John Hartfiel
    • additional notes for FSBL generated with Win SDK
    • changed *.bif
    • bugfix 8GB board parts
    2020-09-222019.2
    2018-03-292017.4
    TE0808-test_board_noprebuilt-vivado_
    2017
    2019.
    4
    2-build_
    07
    14_
    20180329151341
    20200922073159.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2019.
    4
    2-build_
    07
    14_
    20180329151355
    20200922073144.zipJohn Hartfiel
    • new assembly
    variant
    • variants
    2018
    2020-
    01
    03-
    16
    25
    2017
    2019.
    4
    2TE0808-test_board_noprebuilt-vivado_
    2017
    2019.
    4
    2-build_
    04
    8_
    20180116144644
    20200325083246.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2019.
    4
    2-build_
    04
    8_
    20180116144657
    20200325083204.zipJohn Hartfiel
    • Update Board Part for TEBF0808
      • no changes for test board design and minimal board parts
    • script update
    2020
    2018
    -01-
    15
    22
    2017
    2019.
    4
    2TE0808-test_board_noprebuilt-vivado_
    2017
    2019.
    4
    2-build_
    03
    3_
    20180115084954
    20200122142231.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2019.
    4
    2-build_
    03
    3_
    20180115085020
    20200122142208.zipJohn Hartfiel
    • rework Board Part Files
    • 2019.2 update
    • Vitis support
    2019-08-092018.3
    2017-12-202017.2
    TE0808-test_board_noprebuilt-vivado_
    2017
    2018.
    2
    3-build_07_
    20171220192501
    20190809131546.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2018.
    2
    3-build_07_
    20171220192448
    20190809131522.zipJohn Hartfiel
    • Update Board Part Files
    2017-11-22
    • new assembly variants
    2019-05-062018.3
    2017.2
    TE0808-test_board_noprebuilt-vivado_
    2017
    2018.
    2
    3-build_05_
    20171122080211
    20190507124141.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2018.
    2
    3-build_05_
    20171122080228
    20190507124130.zipJohn Hartfiel
    • Update Board Part CSV File
    • Regenerate design
    2017-11-16
    • custom FSBL
    2018-07-112018
    2017
    .2TE0808-test_board_noprebuilt-vivado_
    2017
    2018.2-build_
    05
    02_
    20171116151545
    20180711143743.zip
    TE0808-test_board
    _noprebuilt
    -vivado_
    2017
    2018.2-build_
    05
    02_
    20171116151600
    20180711143702.zipJohn Hartfiel
    • Update Board Part CSV File with new Flash assembly variants
    • additional notes for FSBL generated with Win SDK
    • changed *.bif
    2018-03-292017.4
    2017-11-132017.2
    TE0808-test_board-vivado_2017.
    2
    4-build_
    05
    07_
    20171113140954
    20180329151341.zip
    TE0808-test_board_noprebuilt-vivado_2017.
    2
    4-build_
    05
    07_
    20171113141908
    20180329151355.zipJohn Hartfiel
    • initial release

    Release Notes and Know Issues

    Page properties
    hiddentrue
    idComments
    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues
    IssuesDescriptionWorkaroundTo be fixed versionQSPI FlashFlash programming is not supported with boot mode QSPI or SD.
    If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
    --
    • new assembly variant
    2018-01-162017.4TE0808-test_board-vivado_2017.4-build_04_20180116144644.zip
    TE0808-test_board_noprebuilt-vivado_2017.4-build_04_20180116144657.zip    		John Hartfiel
    • Update Board Part for TEBF0808
      • no changes for test board design and minimal board parts
    2018-01-152017.4TE0808-test_board-vivado_2017.4-build_03_20180115084954.zip
    TE0808-test_board_noprebuilt-vivado_2017.4-build_03_20180115085020.zip    		John Hartfiel
    • rework Board Part Files
    2017-12-202017.2

    TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

    		John Hartfiel
    • Update Board Part Files
    2017-11-222017.2TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip    		John Hartfiel
    • Update Board Part CSV File
    • Regenerate design
    2017-11-162017.2

    TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip

    		John Hartfiel
    • Update Board Part CSV File with new Flash assembly variants
    2017-11-132017.2TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip    		John Hartfiel
    • initial release



    Release Notes and Know Issues

    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware
    SoftwareVersionNoteVitis2021.2needed, Vivado is included into Vitis installationHardware

    Page properties
    hiddentrue
    idComments
    Notes :
      • list of hardware which was used to generate the design
      • mark the module and carrier board, which was used tested with an *
    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed
    scroll-titleanchor
    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Issues
    DescriptionWorkaroundTo be fixed version
    Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
    QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
    		If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
    		--


    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design
    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SoftwareVersionNote
    Vitis2023.2needed, Vivado is included into Vitis installation



    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *
    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:

    15eg
    Expand
    titleExpand List
    Scroll Title
    anchorTable_HWM
    title-alignmentcenter
    titleHardware Modules

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
    TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado          
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado        
    TE0808-04-06EG-1E36eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
    TE0808-04-06EG-1EE6eg_1e_4gbREV044GB128MBNANANA
    TE0808-04-09EG-1EA9eg_1e_2gbREV042GB64MBNANANA
    TE0808-04-09EG-1EB9eg_1e_4gbREV044GB64MBNANANA
    TE0808-04-09EG-1ED9eg_1e_4gbREV044GB64MBNA1 mm connectorsNA
    TE0808-04-09EG-1EE9eg_1e_4gbREV044GB128MBNANANA
    TE0808-04-09EG-1EL9eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
    TE0808-04-09EG-2IB9eg_2i_4gbREV044GB64MBNANANA
    TE0808-04-09EG-2IE9eg_2i_4gbREV044GB128MBNANANA
    TE0808-04-6BE21-A6eg_1e_4gbREV044GB128MBNANANA
    TE0808-04-6BE21-L6eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
    TE0808-04-6BI21-A6eg_1i_4gbREV044GB128MBNANANA
    TE0808-04-6BI21-X6eg_1i_4gbREV044GB128MBNANAU41 replaced with schottky diodes
    TE0808-04-6GI21-L6eg_2i_4gbREV044GB128MBNA1 mm connectorsNA
    TE0808-04-9BE21-A9eg_1e_4gbREV044GB128MBNANANA
    TE0808-04-9BE21-L9eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
    TE0808-04-9GI21-A9eg_2i_4gbREV044GB128MBNANANA
    TE0808-04-15EG-1EB15eg_1e_4gbREV044GB64MBNANANA
    TE0808-04-15EG-1EE15eg_1e_4gbREV044GB128MBNANANA
    TE0808-04-BBE21-A15eg_1e_4gbREV044GB128MBNANANA
    TE0808-05-6BE21-A6eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-6BE21-F6eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-6BE21-AK6eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-6BE21-L6eg
    		Table_HWM
    title-alignmentcenter
    titleHardware Modules
    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
    TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                    
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado             
    TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IE*  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6GI21-L   6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9GI21-A   9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9BE21-A   9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-6BE21-L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6BE21-A   6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9BE21-L   9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-BBE21-A   15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-6BI21-X   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-6BE21-L   6eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-6BE21-A   6eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-6BI21-D   6eg_1i_4gb   REV05       4GB      128MB      NA         1 mm connectorsSoC without encryption               
    TE0808-05-6BI21-X   6eg_1i_4gb   REV05       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-6BI41-X   6eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-9BE21-A   9eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9BE21-L   9eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-9BI41-X   9eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-9GI21-A   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9GI21-C   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               SoC without encryption               
    TE0808-05-BBE21-A   15eg_1e_4gb  REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-BBE21-L   15eg_1e_4gb  REV05       4GB      128MB      NA         1 mm connectorsNA                                     

    TE0808-05-S002

    _1e_4gbREV054GB128MBNA1 mm connectorsNA
    CAO
    TE0808-05-6BI21-
    S003 
    D
    15eg
    6eg_
    1e
    1i_4gbREV054GB128MBNA
    NA
    1 mm connectorsSoC without encryption
    CAO
    TE0808-05-6BI21-
    S005 
    X
    9eg
    6eg_
    2i
    1i_
    4gb 
    4gbREV054GB128MBNANA
    CAO
    U41 replaced with schottky diodes
    TE0808-05-
    S004 
    6BI41-X
    9eg
    6eg_
    2i
    1i_
    4gb 
    8gbREV05
    4GB
    8GB128MBNANA
    CAO
    Single Die DDR; U41 replaced with schottky diodes
    TE0808-05-
    6BE21
    9BE21-
    AK
    A
    6eg
    9eg_1e_
    4gb 
    4gbREV054GB128MBNANANA
    TE0808-05-9BE21-
    LK
    AK9eg_1e_
    4gb 
    4gbREV054GB128MBNA1 mm connectorsNA
    TE0808-05-
    9GI21
    9BE21-
    AK
    AZ9eg_
    2i
    1e_
    4gb 
    4gbREV054GB128MBNA
    NA
    1 mm connectorsNA
    TE0808-05-
    BBE21
    9BE21-
    AK
    KZ
    15eg
    9eg_1e_4gbREV054GB128MBNA
    NA
    1 mm connectorsNA
    TE0808-05-9BE21-
    S006
    L9eg_
    2i
    1e_
    4gb 
    4gbREV054GB128MBNA
    NACAO

    *used as reference

    Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this board part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
    anchorTable_HWC
    title-alignmentcenter
    titleHardware Carrier
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueCarrier ModelNotesCustom PCB use simple Board Part files, if MIO connected is different to TEBF0808TEBF0808*Used as reference carrier.TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design

    *used as reference

    Additional HW Requirements:

    Scroll Title
    anchorTable_AHW
    title-alignmentcenter
    titleAdditional Hardware
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueAdditional HardwareNotes------

    *used as reference

    Content

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    • content of the zip file
    For general structure and usage of the reference design, see Project Delivery - Xilinx devices

    Design Sources

    Scroll Title
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    TypeLocationNotesVivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_filesVivado Project will be generated by TE ScriptsVitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    1 mm connectorsNA
    TE0808-05-9BE21-LK9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
    TE0808-05-9BE21-LZ9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
    TE0808-05-9BE81-A9eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-9BI41-X9eg_1i_8gbREV058GB128MBNANASingle Die DDR; U41 replaced with schottky diodes
    TE0808-05-9GI21-A9eg_2i_4gbREV054GB128MBNANANA
    TE0808-05-9GI21-AK9eg_2i_4gbREV054GB128MBNANANA
    TE0808-05-9GI21-AZ9eg_2i_4gbREV054GB128MBNANANA
    TE0808-05-9GI21-C9eg_2i_4gbREV054GB128MBNANASoC without encryption
    TE0808-05-9GI21-KZ9eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-BBE21-A15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-BBE21-AK15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-BBE21-AZ15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-BBE21-L15eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
    TE0808-05-BBE81-A15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-BBE81-E15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-BBE81-EK15eg_1e_4gbREV054GB128MBNANANA
    TE0808-05-S0019eg_1e_8gb_DREV058GB128MBNACAOCAO;Single Die DDR
    TE0808-05-S00215eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S00315eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0049eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0059eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0069eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0079eg_1e_4gbREV054GB128MBNANACAO
    TE0808-05-S0149eg_1e_4gbREV054GB128MBNANACAO
    TE0808-05-S0169eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0189eg_2e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0199eg_2e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0209eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0219eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0226cg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0256eg_1e_4gb_DREV054GB128MBNACAOCAO
    TE0808-05-S0269eg_2i_4gbREV054GB128MBNACAO:Si5345 not assembledCAO: without PLL
    TE0808-05-S0279eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0299eg_2i_4gbREV054GB128MBNACAOCAO
    TE0808-05-S03315eg_1e_4gbREV054GB128MBNANACAO
    TE0808-05-S03515eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S03615eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0389eg_1e_4gbREV054GB128MBNACAOCAO
    TE0808-05-S0396eg_1e_4gbREV054GB128MBNACAOCAO: without PLL
    TE0808-05-S0416eg_1e_4gb_DREV054GB128MBNACAOCAO

    *used as reference


    Note: Design contains also Board Part Files for TE0808+TEBF0808 configuration, this board part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
    anchorTable_HWC
    title-alignmentcenter
    titleHardware Carrier

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Carrier ModelNotes
    Custom PCBuse simple Board Part files, if MIO connected is different to TEBF0808
    TEBF0808*Used as reference carrier.
    TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design

    *used as reference


    Additional HW Requirements:

    Scroll Title
    anchorTable_AHW
    title-alignmentcenter
    titleAdditional Hardware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Additional HardwareNotes
    ------

    *used as reference

    Content

    Page properties
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    Notes :

    • content of the zip file
    For general structure and usage of the reference design, see Project Delivery - AMD devices

    Design Sources

    Scroll Title
    anchorTable_DS
    title-alignmentcenter
    titleDesign sources

    Scroll Table Layout
    orientationportrait
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    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeLocationNotes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files    		Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation



    Additional Sources

    Scroll Title
    anchorTable_ADS
    title-alignmentcenter
    titleAdditional design sources

    Scroll Table Layout
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    style
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    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeLocationNotes
    ---------


    Prebuilt

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    • prebuilt files
    • Template Table:


      • Scroll Title
        anchorTable_PF
        title-alignmentcenter
        titlePrebuilt files

        Scroll Table Layout
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        style
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        cellHighlightingtrue

        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems



    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Diverse Reports---Report files in different formats
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

    Page properties
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    Reference Design is available on:

    Design Flow

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    Page properties
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    Notes :

    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    Additional Sources

    Scroll Title
    anchorTable_ADS
    title-alignmentcenter
    titleAdditional design sources
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTypeLocationNotes---------

    Prebuilt

    Page properties
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  • prebuilt files
    • Template Table: Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileBoot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

    Debian SD-Image

    *.img

    Debian Image for SD-Card

    Diverse Reports---Report files in different formatsDevice Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project File

    MCS-File

    *.mcs

    Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

    MMI-File

    *.mmi

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    SREC-File

    *.srec

    Converted Software Application for MicroBlaze Processor Systems

    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileDiverse Reports---Report files in different formatsHardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project FileSoftware-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

    Page properties
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    Reference Design is available on:

    Design Flow

    Scroll Ignore
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    Page properties
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    idComments
    Notes :

    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0)  Module selection guide, project creation...prebuilt export...
-- (1)  Create minimum setup of CMD-Files and exit Batch
-- (2)  Create maximum setup of CMD-Files and exit Batch
-- (3)  (internal only) Dev
-- (4)  (internal only) Prod
-- (c)  Go to CMD-File Generation (Manual setup)
-- (d)  Go to Documentation (Web Documentation)
-- (g)  Install Board Files from Xilinx Board Store (beta)
-- (a)  Start design with unsupported Vivado Version (beta)
-- (x)  Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.

      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        Important: Use Board Part Files, which did not end with *_tebf0808


    4. Create hardware description file (.xsa file) and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Generate Programming Files with Vitis

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection

      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    1. Connect JTAG and power on carrier with module

    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

      Code Block
      languagebash
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp hello_te0808


    SD-Boot mode

    This does not work, because SD controller is not selected on PS.

    JTAG

    Load configuration and Application with Vitis Debugger into device

    Usage

    QSPI Boot:

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)

    3. Select QSPI as Boot Mode

      Info

      Note: See TRM of the Carrier, which is used.


    4. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM FSBL from QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR


    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration
    Activated interfaces:
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    TypeNote
    DDR
    QSPIMIO
    UART0MIO, please select other one, if you have connected UART to second controller or other MIO
    SWDT0..1
    TTC0..3


    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Not needed.

    Software Design - Vitis

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    Note:

    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

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    ----------------------------------------------------------

    FPGA Example

    ----------------------------------------------------------

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 20212023.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 20212023.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    ----------------------------------------------------------

    fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 2021.2 FSBL

    General:

  • Modified Files: main.c
    • General Changes:
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation
      • -top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY


    ----------------------------------------------------------

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO
    zynqmp_fsbl

    zynqmp_

    flash

    pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    zynqmp_fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisationName

    hello_te0808

    Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

    Additional Software

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    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:
    No additional software is needed.

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    Document Style update
    DateDocument Revision

    Authors

    		Description

    Page info

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    typeFlat

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    infoTypeModified date
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    typeFlat

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    • 2023.2 release
    • new assembly variants
    2023-06-14v.45Manuela Strücker
    • 2022.2 release
    • new assembly variants
    2023-04-13v.43Manuela Strücker
    • new assembly variants
    2022-09-29v.41Manuela Strücker
    • script update
    • new assembly variants
    2022-09-12v.40Manuela Strücker
    • update board part files compatible to Vivado 2021.2.1
    2022-09-06v.38Manuela Strücker
    • Design Bugfix
    2022-03-16v.36Manuela Strücker
    • Release 2021.2
    2021-05-25v.35Manuela Strücker
    • Document Style update

    2021-05-12

    v.34

    John Hartfiel

    • update board files
    2021-02-05v.33John Hartfiel
    • Release 2020.2
    • Document Style update
    2021-02-05v.31John Hartfiel
    • new assembly variants
    2020-03-25v.28John Hartfiel
    • script update
    2020-01-27v.27John Hartfiel
    • documentation update
    2020-01-22v.26John Hartfiel
    • new assembly variants
    • Release 2019.2
    2019-08-09v.24John Hartfiel
    • new assembly variants
    • small document style update
    2019-05-07v.22John Hartfiel
    • Release 2018.3
    2018-07-11v.21John Hartfiel
    • Release 2018.2

    2018-03-29

    		v.20John Hartfiel
    • new assembly variant
    2018-02-08v.19John Hartfiel
    • Release 2017.4
    2017-12-20v.14John Hartfiel
    • Design Update
    • typo correction on documentation
    2017-11-22v.10John Hartfiel
    • Update assembly versions with new Flash size
    • Update HW Table Name
    • Update Design
    2017-11-14v.6John Hartfiel
    • Release 2017.2
    --all

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    		--


    Legal Notices

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    IN:Legal Notices



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