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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


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Notes :

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2021.2.1
  • QSPI
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
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titleDesign Revision History


DateVivadoProject BuiltAuthorsDescription
2022-
03
09-
16
292021.2.1TE0808-test_board-vivado_2021.2-build_
11
17_
20220316091917
20220928203325.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_
11
17_
202203160919172021-05
20220928203325.zipManuela Strücker
  • 2021.2 release
  • update board files
  • script update
  • new assembly variants
2022-09-12
2020
2021.2.1TE0808-test_board-vivado_
2020
2021.2-build_
5
15_
20210512133121
20220912090608.zip
TE0808-test_board_noprebuilt-vivado_
2020
2021.2-build_
5
15_
20210512133137
20220912090608.zip
John Hartfiel
Manuela Strücker
  • update board part files
2021-02-052020
  • compatible to Vivado 2021.2.1
2022-03-212021.2TE0808-test_board-vivado_
2020
2021.2-build_
0
11_
20210204141911
20220321063547.zip
TE0808-test_board_noprebuilt-vivado_
2020
2021.2-build_
1
11_
202102041428552019
20220321063547.zipJohn Hartfiel
  • 2020.2 update
2020-09-29
  • replace Starterkit FSBL with default one
2022-03-162021.2TE0808-test_board
_noprebuilt
-vivado_
2019
2021.2-build_
15
11_
20200929070740
20220316091917.zip
TE0808-test_board_noprebuilt-vivado_
2019
2021.2-build_
15_20200929070725John Hartfiel
  • bugfix 8GB board parts
2020-09-222019
11_20220316091917.zipManuela Strücker
  • 2021.2 release
  • update board files
2021-05-122020.2TE0808-test_board
_noprebuilt
-vivado_
2019
2020.2-build_
14
5_
20200922073159
20210512133121.zip
TE0808-test_board_noprebuilt-vivado_
2019
2020.2-build_
14
5_
202009220731442020-03-252019
20210512133137.zipJohn Hartfiel
  • new assembly variants
  • update board files
2021-02-052020.2TE0808-test_board
_noprebuilt
-vivado_
2019
2020.2-build_
8
0_
20200325083246
20210204141911.zip
TE0808-test_board_noprebuilt-vivado_
2019
2020.2-build_
8
1_
20200325083204
20210204142855.zipJohn Hartfiel
script
  • 2020.2 update
2020-
01
09-
22
292019.2TE0808-test_board_noprebuilt-vivado_2019.2-build_
3
15_
20200122142231
20200929070740.zip
TE0808-test_board-vivado_2019.2-build_
3
15_
20200122142208.zip2018.3
20200929070725John Hartfiel
  • 2019.2 update
  • Vitis support
2019-08-09
  • bugfix 8GB board parts
2020-09-222019.2TE0808-test_board_noprebuilt-vivado_
2018
2019.
3
2-build_
07
14_
20190809131546
20200922073159.zip
TE0808-test_board-vivado_
2018
2019.
3
2-build_
07
14_
20190809131522
20200922073144.zipJohn Hartfiel
  • new assembly variants
2019
2020-
05
03-
06
25
2018
2019.
3
2TE0808-test_board_noprebuilt-vivado_
2018
2019.
3
2-build_
05
8_
20190507124141
20200325083246.zip
TE0808-test_board-vivado_
2018
2019.
3
2-build_
05
8_
20190507124130
20200325083204.zipJohn Hartfiel
custom FSBL
  • script update
2018
2020-
07
01-
11
22
2018
2019.2TE0808-test_board_noprebuilt-vivado_
2018
2019.2-build_
02
3_
20180711143743
20200122142231.zip
TE0808-test_board-vivado_
2018
2019.2-build_
02
3_
201807111437022018-03-292017.4
20200122142208.zipJohn Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
  • 2019.2 update
  • Vitis support
2019-08-092018.3TE0808-test_board_noprebuilt-vivado_
2017
2018.
4
3-build_07_
20180329151341
20190809131546.zip
TE0808-test_board
_noprebuilt
-vivado_
2017
2018.
4
3-build_07_
20180329151355
20190809131522.zipJohn Hartfiel
  • new assembly
variant
  • variants
2018
2019-
01
05-
16
06
2017
2018.
4
3TE0808-test_board_noprebuilt-vivado_
2017
2018.
4
3-build_
04
05_
20180116144644
20190507124141.zip
TE0808-test_board
_noprebuilt
-vivado_
2017
2018.
4
3-build_
04
05_
201801161446572018-01-152017.4
20190507124130.zipJohn Hartfiel
  • Update Board Part for TEBF0808
    • no changes for test board design and minimal board parts
  • custom FSBL
2018-07-112018.2TE0808-test_board_noprebuilt-vivado_
2017
2018.
4
2-build_
03
02_
20180115084954
20180711143743.zip
TE0808-test_board
_noprebuilt
-vivado_
2017
2018.
4
2-build_
03
02_
20180115085020
20180711143702.zipJohn Hartfiel
  • rework Board Part Files
2017-12-20
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-03-292017.
2
4TE0808-test_board-vivado_2017.
2
4-build_07_
20171220192501
20180329151341.zip
TE0808-test_board_noprebuilt-vivado_2017.
2
4-build_07_
201712201924482017-11-22
20180329151355.zipJohn Hartfiel
  • Update Board Part Files
  • new assembly variant
2018-01-162017.
2
4TE0808-test_board-vivado_2017.
2
4-build_
05
04_
20171122080211
20180116144644.zip
TE0808-test_board_noprebuilt-vivado_2017.
2
4-build_
05
04_
20171122080228
20180116144657.zipJohn Hartfiel
  • Update Board Part
CSV File
  • Regenerate design
  • 2017-11-16
    • for TEBF0808
      • no changes for test board design and minimal board parts
    2018-01-152017.
    2
    4TE0808-test_board-vivado_2017.
    2
    4-build_
    05
    03_
    20171116151545
    20180115084954.zip
    TE0808-test_board_noprebuilt-vivado_2017.
    2
    4-build_
    05
    03_
    20171116151600
    20180115085020.zipJohn Hartfiel
    Update
    • rework Board Part
    CSV File with new Flash assembly variants
    • Files
    2017-
    11
    12-
    13
    202017.2

    TE0808-test_board-vivado_2017.2-build_

    05

    07_

    20171113140954

    20171220192501.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_

    05

    07_

    20171113141908

    20171220192448.zip

    John Hartfiel
    • initial release
    Release Notes
    • Update Board Part Files
    2017-11-222017.2TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip
    John Hartfiel
    • Update Board Part CSV File
    • Regenerate design
    2017-11-162017.2

    TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip

    John Hartfiel
    • Update Board Part CSV File with new Flash assembly variants
    2017-11-132017.2TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip
    TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip
    John Hartfiel
    • initial release


    Release Notes and Know Issues

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    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed
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    titleKnown Issues


    IssuesDescriptionWorkaroundTo be fixed versionWorkaroundTo be fixed version
    Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
    QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
    If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
    --


    Requirements

    Software

    Page properties
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    Notes :

    • list of software which was used to generate the design
    Scroll Table Layout
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    titleSoftware


    SoftwareVersionNote
    Vitis2021.2.1needed, Vivado is included into Vitis installation



    Hardware

    Page properties
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    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *
    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:

    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue Scroll Title
    anchorTable_HWM
    title-alignmentcenter
    titleHardware Modules
    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotesTE0808-ES1          es1_2gb      REV03|REV02 2GB      

    modules:

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    titleHardware Modules


    -ES2          2GB      Not longer supported by vivado                    04REV04       04REV04       6BE21L   6eg1 mm connectors6BE21A   6egNA               9BI41-X   9eg1i8gb   REV05       8GB      128MB      NA         U41 replaced with schottky diodes    9GI21-A   9eg2i4gb   REV05       4GB      128MB      NA         NA               NA                                     9GI21-C   4gb   REV05       4GB      128MB      NA         NA               SoC without encryption               BBE21-A   15eg1e4gb  REV05       4GB      128MB      NA         NA               NA                                     BBE21L   15eg4gb  REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
    TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                    
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado             
    TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               Not longer supported by vivado       NA                                     
    TE0808es2_2gb      REV04|REV03 -04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               1 mm connectorsNA                                     
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               Not longer supported by vivado             NA                                     
    TE0808-04-09EG15EG-1EA  1EB  9eg15eg_1e_2gb   4gb  REV04       2GB      4GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EB  1EE  9eg_1e_4gb   REV04       4GB      64MB       128MB      NA         NA               NA                                     
    TE0808-04-09EG-1ED  1EL  9eg_1e_4gb   REV04       4GB      64MB       128MB      NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IB  2IE* 9eg_2i_4gb   REV04       4GB      64MB       128MB      NA         NA               NA                                     
    TE0808-04-15EG-1EB  1EE  15eg_1e_4gb  REV04       4GB      64MB       128MB      NA         NA               NA                                     
    TE0808-04-09EG06EG-1EE  9eg6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-09EG06EG-1EL  1E3  9eg6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-09EG6GI21-2IE*  L   9eg6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-15EG9GI21-1EE  A   15eg9eg_1e2i_4gb  4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG9BE21-1EE  A   6eg9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG6BE21-1E3  L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6GI216BE21-L   A   6eg_2i1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA               NA                                     
    TE0808-04-6BI219BE21-A   L   6eg9eg_1i1e_4gb   REV04       4GB      128MB      NA         NA               1 mm connectorsNA                                     
    TE0808-04-9GI21BBE21-A   9eg15eg_2i1e_4gb   4gb  REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9BE216BI21-A   X   9eg6eg_1e1i_4gb   REV04       4GB      128MB      NA         NA               NA                                     U41 replaced with schottky diodes    
    TE0808-05-6BE21-L   6eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-6BE21-A   6eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-0405-9BE216BI21-L   D   9eg6eg_1e1i_4gb   REV04       REV05       4GB      128MB      NA         1 mm connectorsNA                                     SoC without encryption               
    TE0808-0405-BBE216BI21-A   X   15eg6eg_1e1i_4gb  4gb   REV04       REV05       4GB      128MB      NA         NA               NA                                     U41 replaced with schottky diodes    
    TE0808-0405-6BI216BI41-X   6eg_1i_4gb   8gb   REV04       REV05       4GB      8GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-9BE21-A   9eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9BE21-L   9eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-6BI219BI41-D   X   6eg9eg_1i_4gb   8gb   REV05       4GB      8GB      128MB      NA         1 mm connectorsSoC without encryption               NA               U41 replaced with schottky diodes    
    TE0808-05-6BI219GI21-X   A   6eg9eg_1i2i_4gb   REV05       4GB      128MB      NA         NA               U41 replaced with schottky diodes    NA                                     
    TE0808-05-6BI419GI21-X   C   6eg9eg_1i2i_8gb   4gb   REV05       8GB      4GB      128MB      NA         NA               U41 replaced with schottky diodes    SoC without encryption               
    TE0808-05-9BE21BBE21-A   9eg15eg_1e_4gb   4gb  REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9BE21BBE21-L   9eg15eg_1e_4gb   4gb  REV05       4GB      128MB      NA         1 mm connectorsNA                                     

    TE0808-05-

    S002

    15eg_

    1e_

    4gb

    REV054GB128MBNANA               NACAO
    TE0808-05-S003 15eg_1e_4gbREV054GB128MBNANACAO
    TE0808-05-S005 9eg_2i_4gb REV054GB128MBNANACAO
    TE0808-05-S004 9eg_2i_4gb REV054GB128MBNANACAO
    TE0808-05-6BE21-AK6eg_1e_4gb REV054GB128MBNANANA
    TE0808-05-9BE21-S002LK15eg9eg_1e_4gb4gb REV054GB128MBNA1 mm connectorsNACAO
    TE0808-05-S003 9GI21-AK15eg9eg_1e2i_4gb4gb REV054GB128MBNANACAONA
    TE0808-05-BBE21-S005 AK9eg15eg_2i1e_4gb 4gbREV054GB128MBNANACAONA
    TE0808-05-S004 S0069eg_2i_4gb REV054GB128MBNANACAO
    TE0808-05-6BE21-AKS0166eg9eg_1e_4gb 4gbREV054GB128MBNANANACAO
    TE0808-05-9BE21-LKS0189eg_1e2e_4gb 4gbREV054GB128MBNA1 mm connectorsNANACAO
    TE0808-05-9GI21-AKS0199eg_2i2e_4gb 4gbREV054GB128MBNANANACAO
    TE0808-05-BBE21-AKS02115eg9eg_1e2i_4gbREV054GB128MBNANANACAO
    TE0808-05-S006S0229eg6cg_2i1e_4gb 4gbREV054GB128MBNANACAO

    *used as reference

    Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this board part files are not used for this reference design.

    Design supports following carriers:

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    Carrier ModelNotes
    Custom PCB use simple Board Part files, if MIO connected is different to TEBF0808
    TEBF0808*Used as reference carrier.
    TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design

    *used as reference


    Additional HW Requirements:

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    Additional HardwareNotes
    ------

    *used as reference

    Content

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    Notes :

    • content of the zip file
    For general structure and usage of the reference design, see Project Delivery - Xilinx devices

    Design Sources

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    TypeLocationNotes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files
    Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation



    Additional Sources

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    ---------


    Prebuilt

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    • prebuilt files
    • Template Table:

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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems



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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Diverse Reports---Report files in different formats
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
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      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        Important: Use Board Part Files, which did not end with *_tebf0808


    4. Create hardware description file (.xsa file) and export to prebuilt folder

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      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Generate Programming Files with Vitis

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      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp hello_te0808


    SD-Boot mode

    This does not work, because SD controller is not selected on PS.

    JTAG

    Load configuration and Application with Vitis Debugger into device

    Usage

    QSPI Boot:

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select QSPI as Boot Mode

      Info

      Note: See TRM of the Carrier, which is used.


    4. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM FSBL from QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR


    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration
    Activated interfaces:


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    TypeNote
    DDR
    QSPIMIO
    UART0MIO, please select other one, if you have connected UART to second controller or other MIO
    SWDT0..1
    TTC0..3


    Constrains

    Basic module constrains

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    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Not needed.

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

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    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 2021.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 2021.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    fsbl

    TE modified 2021.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    zynqmp_fsbl_flash

    TE modified 2021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    hello_te0808

    Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

    Additional Software

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    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:
    No additional software is needed.

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Note this list must be only updated, if the document is online on public doc!
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      • Metadata is only used of compatibility of older exports


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    DateDocument Revision

    Authors

    Description

    Page info
    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    Document Style update

    • script update
    • new assembly variants
    2022-09-12v.40Manuela Strücker
    • update board part files compatible to Vivado 2021.2.1
    2022-09-06v.38Manuela Strücker
    • Design Bugfix
    2022-03-16v.36Manuela Strücker
    • Release 2021.2
    2021-05-25v.35Manuela Strücker
    • Document Style update

    2021-05-12

    v.34

    John Hartfiel

    • update board files
    2021-02-05v.33John Hartfiel
    • Release 2020.2
    • Document Style update
    2021-02-05v.31John Hartfiel
    • new assembly variants
    2020-03-25v.28John Hartfiel
    • script update
    2020-01-27v.27John Hartfiel
    • documentation update
    2020-01-22v.26John Hartfiel
    • new assembly variants
    • Release 2019.2
    2019-08-09v.24John Hartfiel
    • new assembly variants
    • small document style update
    2019-05-07v.22John Hartfiel
    • Release 2018.3
    2018-07-11v.21John Hartfiel
    • Release 2018.2

    2018-03-29

    v.20John Hartfiel
    • new assembly variant
    2018-02-08v.19John Hartfiel
    • Release 2017.4
    2017-12-20v.14John Hartfiel
    • Design Update
    • typo correction on documentation
    2017-11-22v.10John Hartfiel
    • Update assembly versions with new Flash size
    • Update HW Table Name
    • Update Design
    2017-11-14v.6John Hartfiel
    • Release 2017.2
    --all

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    --


    Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices



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