Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents
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Overview
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General Design description
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Simple MicroBlaze Design with Hello TE0711 and LED control via VIO.
Key Features
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Excerpt
MicroBlaze
LED
QSPI
UART
Revision History
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Release Notes and Know Issues
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<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
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File
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File-Extension
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Description
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template (note: inner scroll ignore/only only with drawIO object):
Scroll Title
anchor
Figure_xyz
title
Text
Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use
Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Simple MicroBlaze Design with Hello TE0711 and LED control via VIO. Refer to http://trenz.org/te0711-info for the current online version of this manual and other available documentation.
Key Features
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Notes :
Add basic key futures, which can be tested with the design
Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
Additional Sources
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Additional design sources
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Type
Location
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Prebuilt
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Notes :
prebuilt files
Template Table:
Scroll Title
anchor
Table_PF
title
Prebuilt files
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.xsa
Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
Scroll Title
anchor
Table_PF
title
Prebuilt files (only on ZIP with prebult content)
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
File
File-Extension
Description
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.xsa
Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Important set new Vivado version link on every Design update of new vivado version!
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell: Image Added
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
(optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" Note: Select correct one, see alsoTE Board Part Files
Create XSA and export to prebuilt folder
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate ApplicationFiles with Vitis
Run on Vivado TCL: TE::sw_run_vitis -all Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Copy Application (hello_te0711.elf) into \firmware\microblaze_0\
Regenerate Design:
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
(alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.
Launch
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Note:
Programming and Startup procedure
Programming
Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell: Image Removed
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_createto start "Module Selection Guide"
Select assembly version
Validate selection
Select Create and open delivery binary folder Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" Note: Select correct one, see TE Board Part FilesCreate HDF and export to prebuilt folder Run on Vivado TCLor if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::hwpr_buildprogram_design flash -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate ApplicationFiles with HSI/SDK
Run on Vivado TCL: TE::sw_run_hsi Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk Note: See SDK Projects
Copy Application (hello_te0711.elf) into \firmware\microblaze_0\
Regenerate Design:
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
(alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.
Launch
Programming
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Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
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Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
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To get content of older revision got to "Change History" of this page and select older document revision number.
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Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports