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The following table lists all on the FMC connector assigned net names.

	A	B	C	D	E	F	G	H	J	K
1	GND	NetJ2_B1	GND	PG_C2M	GND	PG_M2C	GND		GND
2	SFPB_RD_P	GND	SFPA_TD_P	GND		GND	CLK1_P	GND		GND
3	SFPB_RD_N	GND	SFPA_TD_N	GND		GND	CLK1_N	GND		GND
4	GND		GND	GBTCLK0_P	GND		GND	CLK0_P	GND	CLK2_P
5	GND		GND	GBTCLK0_N	GND		GND	CLK0_N	GND	CLK2_N
6	SFPC_RD_P	GND	SFPA_RD_P	GND		GND	LA00_P	GND		GND
7	SFPC_RD_N	GND	SFPA_RD_N	GND			LA00_N	LA02_P
8	GND		GND	LA01_P	GND		GND	LA02_N	GND
9	GND		GND	LA01_N		GND	LA03_P	GND		GND
10	SFPD_RD_P	GND	LA06_P	GND			LA03_N	LA04_P
11	SFPD_RD_N	GND	LA06_N	LA05_P	GND		GND	LA04_N	GND
12	GND		GND	LA05_N		GND	LA08_P	GND		GND
13	GND		GND	GND			LA08_N	LA07_P
14		GND		LA09_P	GND		GND	LA07_N	GND
15		GND		LA09_N		GND		GND		GND
16	GND		GND	GND
17	GND		GND		GND		GND		GND
18		GND				GND		GND		GND
19		GND		GND
20	GND	GBTCLK1_P	GND		GND		GND		GND
21	GND	GBTCLK1_N	GND			GND		GND		GND
22	SFPB_TD_P	GND		GND
23	SFPB_TD_N	GND			GND		GND		GND
24	GND		GND			GND		GND		GND
25	GND		GND	GND
26	SFPC_TD_P	GND			GND		GND		GND
27	SFPC_TD_N	GND				GND		GND		GND
28	GND		GND	GND
29	GND		GND	TCK	GND		GND		GND
30	SFPD_TD_P	GND	FMC_SCL	TDI		GND		GND		GND
31	SFPD_TD_N	GND	FMC_SDA	TDO
32	GND		GND	3P3VAUX	GND		GND		GND
33	GND		GND	TMS		GND		GND		GND
34		GND	GA0
35		GND	12V	GA1	GND		GND		GND
36	GND		GND	3P3V		GND		GND		GND
37	GND		12V	GND
38		GND	GND	3P3V	GND		GND		GND
39		GND	3P3V	GND	VADJ	GND	VADJ	GND		GND
40	GND		GND	3P3V	GND	VADJ	GND	VADJ	GND

Table 8: HPC FMC Connector pin assignment.

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There is a Silicon Labs I²C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module. Programming can be done using I²C via PIN header J1. The I²C bus is also routed to the MAX10 FPGA.

Si5345A Pin	Signal Name / Description	Connected To	Direction	Note	Default
IN0	Reference input clock.	U1	Input	25.000000 MHz oscillator, Si8208AI
IN1	-	Not connected.	Input	Not used.
IN2	-	Not connected.	Input	Not used.
IN3	CLK2	J2-K4/K5	Input	HPC FMC configured as C2M clock.
A1	-	GND	Input	I²C slave device address LSB.
XAXB	-	Y1	Input	54.0000 MHz XTAL CX3225SB
OUT0	CLKPLL2F	U5-H6/G5	Output	FPGA bank 2.	25MHz
OUT1	-	Not connected.	Output	Not used.	---
OUT2	GBTCLK1	J2-B20/B21	Output	M2C via HPC FMC.	125MHz
OUT3	-	Not connected.	Output	Not used.	---
OUT4	-	Not connected.	Output	Not used.	---
OUT5	-	Not connected.	Output	Not used.	---
OUT6	-	Not connected.	Output	Not used.	---
OUT7	GBTCLK0	J2-D4/D5	Output	M2C via HPC FMC.	156.25MHz
OUT8	CLK0	J2-H4/H5	Output	M2C via HPC FMC.	156.25MHz
OUT9	CLK1	J2-G2/G3	Output	M2C via HPC FMC.	125MHz

Table 9: Programmable clock generator inputs and outputs.

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Date

Revision

Contributors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Martin Rohrmüller

Page info

prefix
infoType	Current version

Updated Table 15 and 17 to Rev02.

Added FMC connector pin assignment (Table 8).

	v.

32


type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

add default CLK values also to SI section
changes on document change history style

2018-08-24

v.38

Martin Rohrmüller

Updated Table 15 and 17 to Rev02.
Added FMC connector pin assignment (Table 8).

2018-06-15

v.32

Martin Rohrmüller

Initial document.

---

allJan Kumann, John Hartfiel

Page info

infoType	Modified users
type	Flat
showVersions	false

---

Table 18: Document change history.

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Trenz Electronic Documentation

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