Page History

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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Date	Version	Changes	Author
2022-01-25	3.1.10	removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin corrected Boot Source File in Boot Script-File	ma
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.src description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

Custom_table_size_100

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Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

...

Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

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Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Example shows, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze with Linux example.

Refer to http://trenz.org/te0841-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

Add basic key features, which can be tested with the design

Excerpt
Vitis/Vivado 2021.2 PetaLinux MicroBlaze I2C UART Flash FMeter SI5338 initialisation with MCS

Revision History

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Notes :

add every update file on the download
add design changes on description

Scroll Title

anchor	Table_DRH
title-alignment	center
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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cellHighlighting	true

Date	Vivado	Project Built	Authors	Description
2022-05-06	2021.2	TE0841-test_board-vivado_2021.2-build_14_2022050609534320220506142737.zip TE0841-test_board_noprebuilt-vivado_2021.2-build_14_2022050609534320220506142737.zip	Waldemar Hanemann	new spi bootloader by Henrik Brix Andersen fixed SC0841 bugs
2020-05-13	2019.2	TE0841-test_board-vivado_2019.2-build_11_20200513071943.zip TE0841-test_board_noprebuilt-vivado_2019.2-build_11_20200513072026.zip	John Hartfiel	new Assembly variants add Linux
2018-06-21	2017.4	TE0841-test_board_noprebuilt-vivado_2017.4-build_11_20180621164459.zip TE0841-test_board-vivado_2017.4-build_11_20180621164432.zip	John Hartfiel	REV02 Board parts new SI5338 configuration (default REV02) change xilisf_v5_9 for N25Q512A11G1240E support Some changes on block design
2018-05-15	2017.4	TE0841-test_board_noprebuilt-vivado_2017.4-build_08_20180515144542.zip TE0841-test_board-vivado_2017.4-build_08_20180515144523.zip	John Hartfiel	initial release

Release Notes and Know Issues

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Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortEnabled	false
cellHighlighting	true

Issues	Description	Workaround	To be fixed version
No known issues	---	---	---

Requirements

Software

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Notes :

list of software which was used to generate the design

Scroll Title

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title-alignment	center
title	Software

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
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Software	Version	Note
Vitis	2021.2	needed, Vivado is included into Vitis installation
PetaLinux	2021.2	needed
SI ClockBuilder Pro	---	optional

Hardware

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Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
TE0841-01-035-1C	01_35_1c_1gb	REV01	1GB	32MB	NA	NA	NA
TE0841-01-035-1I	01_35_1i_1gb	REV01	1GB	32MB	NA	NA	NA
TE0841-01-035-2I	01_35_2i_1gb	REV01	1GB	32MB	NA	NA	NA
TE0841-01-040-1C	01_40_1c_1gb	REV01	1GB	32MB	NA	NA	Serial number 512479 up tp 512474 has same 64MB Flash like REV02
TE0841-01-040-1I	01_40_1i_1gb	REV01	1GB	32MB	NA	NA	NA
TE0841-02-035-1C	02_35_1c_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-035-1I	02_35_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-035-2I	02_35_2i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-040-1C	02_40_1c_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-040-1I	02_40_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-040-1IL	02_40_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-31C21-A	02_35_1c_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-31I21-A	02_35_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-32I21-A	02_35_2i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-41C21-A	02_40_1c_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-41I21-A	02_40_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed
TE0841-02-41I21-L	02_40_1i_2gb	REV02	2GB	64MB	NA	NA	PLL programmed

^*used as reference

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title-alignment	center
title	Hardware Carrier

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortEnabled	false
cellHighlighting	true

Carrier Model	Notes
TE0701
TE0703
TE0705
TE0706	used as reference carrier
TEBA0841

^*used as reference

Additional HW Requirements:

Scroll Title

anchor	Table_AHW
title-alignment	center
title	Additional Hardware

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct typ
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI
heat sink	Heat sink is recommended urgently

^*used as reference

Content

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Notes :

content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices

Design Sources

Scroll Title

anchor	Table_DS
title-alignment	center
title	Design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux	<project folder>\os\petalinux	PetaLinux template with current configuration

Additional Sources

Scroll Title

anchor	Table_ADS
title-alignment	center
title	Additional design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
SI5338	<project folder>\misc\Si5338	SI5338 Project with current PLL Configuration

Prebuilt

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Notes :

prebuilt files

Template Table:

Scroll Title

anchor	Table_PF
title-alignment	center
title	Prebuilt files

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

Scroll Title

anchor	Table_PF
title-alignment	center
title	Prebuilt files (only on ZIP with prebuilt content)

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repeatTableHeaders	default
style
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cellHighlighting	true

File	File-Extension	Description
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.xsa	Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0841 "Test Board" Reference Design

Design Flow

Scroll Ignore

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scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

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Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Scroll Ignore

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Note:

Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)

Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
TE::pr_program_flash -swapp u-boot
Note
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
Reboot (if not done automatically)

SD-Boot mode

Not used on this Example.

JTAG

Not used on this example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Select SD Card QSPI as Boot Mode (or QSPI - depending on step 1)

Info
Note: See TRM of the Carrier, which is used.

Tip

Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr

Power On PCB

Expand

title	boot process

1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

FPGA Loads Bitfile from Flash

2. MCS Firmware configure SI5338 and starts Microblaze

3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR

43. U-boot loads Linux (image.ub) from SD/QSPI/... Linux from QSPI Flash into DDR

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This step depends on Xilinx Device/Hardware

for Zynq-7000 series

1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for ZynqMP???

1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for Microblaze with Linux

1. FPGA Loads Bitfile from Flash,

2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

4. U-boot loads Linux from QSPI Flash into DDR

for native FPGA

...

Linux

Open Serial Console (e.g. putty)
- Speed: 1152009600
- select COM Port
  Info
  Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block
language bash
theme Midnight
petalinux login: root Password: root
Info
Note: Wait until Linux boot finished
Boot process takes a while, please wait...
Expand
title Boot linux
Image Added
You can use Linux shell now.
code

Vivado HW Manager

language

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bash

hidden

theme

true

Midnight

i2cdetect -y -r 0	(check I2C 1 Bus)
dmesg | grep rtc	(RTC check)
udhcpc				(ETH0 check)
lsusb				(USB check)

Option Features

Webserver to get access to Zynq
- insert IP on web browser to start web interface
init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

id	Comments

Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..

Vivado HW Manager

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id	Comments

Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
- SI5338 CLKs:
  - Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz
  - expected CLK Frequency...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

Control:

Monitoring:
- SI will be configured with MCS firmware, default all off on PCB REV01, PCB REV02 SI5338 will be preconfigured.
- LED control via VIO
- MGT CLK Freq can be changed over BUFG_GT control signals divider
- MCS Reset possible via VIO
- MIG Reset is possible over VIO
- MCS can be disabled over VIO (For PCB REV01 MCS is enabled, fpr PCB REV02 MCS is disabled by default VIO)
Monitoring:
- Set radix from VIO signals (fm_si...) to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz

Scroll Title

anchor	Figure_

Scroll Title

anchor	Figure_VHM
title-alignment	center
title	Vivado Hardware Manager

Image Added

System Design - Vivado

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scroll-docbook	true
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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title

anchor	Figure_BD
title-alignment	center
title	Block Design

PS Interfaces

PCB

Image Added

Note: REV01 has SI5338 programming default enabled and REV02 default disabled. SI5338 of REV02 is preprogrammed

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

Scroll Title

anchor	Table_PSI
title-alignment	center
title	PS Interfaces

Constraints

Basic module constraints

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTypeNoteDDRQSPIMIOSD0MIOSD1MIOI2C0MIOUART0MIOGPIO0MIOSWDT0..1TTC0..3GEM3MIOUSB0MIO

Constraints

Basic module constraints

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG_VOLTAGE 3.3.CONFIGRATE 69 [current_design]
set_property CFGBVS VCCOGND [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESSVOLTAGE TIMESTAMP1.8 [current_design]

Design specific constraints

Code Block

language	ruby
title	_i_io.xdc


set_property PACKAGECONFIG_PINMODE K2SPIx4 [get_ports {fclk[0]}]current_design]
set_property IOSTANDARD LVCMOS18BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [get_ports {fclk[0]}]current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - Vitis

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scroll-eclipsehelp	true
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id	Comments

Note:

optional chapter separate
sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2021.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

...

Software Design - PetaLinux

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Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

No changes.

Change platform-top.h:

Code Block

language	js

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

No changes.

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

No additional software is needed.

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

SI5345

File location "<project folder>\misc\Si5345\Si5345-*.slabtimeproj"

General documentation how you work with this project will be available on Si5345

App. A: Change History and Legal Notices

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_dch
title-alignment	center
title	Document change history.

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidths2*,*,3*,4*sortByColumn1sortEnabledfalsecellHighlightingtrueDateDocument Revision

Authors

Description Page infomodified-datemodified-datedateFormatyyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

change list

--all

Page info

infoType	Modified users
dateFormat	yyyy-MM-dd
type	Flat

--

Legal Notices

Include PageIN:Legal NoticesIN:Legal Notices

_ _ _ _ _ _ _ _ _ _WALDI HIER !!! STARTET ALTE DOC !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Page properties

hidden	true
id	Comments

Template Revision 2.7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

HTML

<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

Page properties

hidden	true
id	Comments

Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constraints

Code Block

language	ruby
title	_i_io.xdc

set_property PACKAGE_PIN AD28 [get_ports sc0841_interface_ddr4_par_44]
set_property PACKAGE_PIN C28 [get_ports sc0841_interface_ddr4_par_46]
set_property PACKAGE_PIN AD20 [get_ports sc0841_interface_en_ddr4pwr]
set_property PACKAGE_PIN AH23 [get_ports sc0841_interface_en_gtpwr]
set_property PACKAGE_PIN AF24 [get_ports sc0841_interface_en_osc]
set_property PACKAGE_PIN AB20 [get_ports sc0841_interface_pll_scl_io]
set_property PACKAGE_PIN P28 [get_ports sc0841_interface_xio_io]
set_property PACKAGE_PIN AE20 [get_ports sc0841_interface_pg_ddr]
set_property PACKAGE_PIN AH22 [get_ports sc0841_interface_pg_gt]
set_property PACKAGE_PIN AB19 [get_ports sc0841_interface_pll_sda_io]

set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_44]
set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_46]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_ddr4pwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_gtpwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_osc]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports sc0841_interface_xio_io]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_ddr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_gt]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_sda_io]

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

Scroll Title

anchor	Table_xyz
title	Text

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Example

Comment

1

2

...

Scroll pdf ignore

Overview

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze with Linux example.

Refer to http://trenz.org/te0841-info for the current online version of this manual and other available documentation.

Key Features

Page properties

hidden	true
id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 2019.2 PetaLinux MicroBlaze I2C UART Flash FMeter SI5338 initialisation with MCS

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

Scroll Title

anchor	Table_DRH
title	Design Revision History

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Date

Vivado

Project Built

Authors

Description

2020-0513

2019.2

TE0841-test_board-vivado_2019.2-build_11_20200513071943.zip

TE0841-test_board_noprebuilt-vivado_2019.2-build_11_20200513072026.zip

John Hartfiel

new Assembly variants
add Linux

2018-06-21

2017.4

TE0841-test_board_noprebuilt-vivado_2017.4-build_11_20180621164459.zip
TE0841-test_board-vivado_2017.4-build_11_20180621164432.zip

John Hartfiel

REV02 Board parts
new SI5338 configuration (default REV02)
change xilisf_v5_9 for N25Q512A11G1240E support
Some changes on block design

2018-05-15

2017.4

TE0841-test_board_noprebuilt-vivado_2017.4-build_08_20180515144542.zip

TE0841-test_board-vivado_2017.4-build_08_20180515144523.zip

John Hartfiel

initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title	Known Issues

Scroll Table Layout

orientation

portrait

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ASC

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false

cellHighlighting

true

Issues

Description

Workaround

To be fixed version

---

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title	Software

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ASC

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Software

Version

Note

Vitis

2019.2

needed
Vivado is included into Vitis installation

PetaLinux

2019.2

needed

SI ClockBuilder Pro

---

optional

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title

anchor	Table_HWM
title	Hardware Modules

Scroll Table Layout

orientation

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ASC

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true

Module Model

Board Part Short Name

PCB Revision Support

DDR

QSPI Flash

EMMC

Others

Notes

TE0841-01-035-1C

01_35_1c_1gb

REV01

1GB

32MB

NA

TE0841-01-035-1I

01_35_1i_1gb

REV01

1GB

32MB

NA

TE0841-01-035-2I

01_35_2i_1gb

REV01

1GB

32MB

NA

TE0841-01-040-1C

01_40_1c_1gb

REV01

1GB

32MB

NA

Serial number 512479 up tp 512474 has same 64MB Flash like REV02

TE0841-01-040-1I

01_40_1i_1gb

REV01

1GB

32MB

NA

TE0841-02-035-1C

02_35_1c_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-035-1I

02_35_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-035-2I

02_35_2i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-040-1C

02_40_1c_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-040-1I

02_40_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-040-1IL

02_40_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-31C21-A

02_35_1c_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-31I21-A

02_35_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-32I21-A

02_35_2i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-41C21-A

02_40_1c_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-41I21-A

02_40_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

TE0841-02-41I21-L

02_40_1i_2gb

REV02

2GB

64MB

NA

PLL programmed

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title	Hardware Carrier

Scroll Table Layout

orientation

portrait

sortDirection

ASC

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default

style

widths

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1

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false

cellHighlighting

true

Carrier Model

Notes

TE0701

TE0703

TE0705

TE0706

used as reference carrier

TEBA0841

Additional HW Requirements:

Scroll Title

anchor	Table_AHW
title	Additional Hardware

Scroll Table Layout

orientation

portrait

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ASC

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false

cellHighlighting

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Additional Hardware

Notes

USB Cable for JTAG/UART

Check Carrier Board and Programmer for correct typ

XMOD Programmer

Carrier Board dependent, only if carrier has no own FTDI

heat sink

Heat sink is recommended urgently

Content

Page properties

hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Scroll Title

anchor	Table_DS
title	Design sources

Scroll Table Layout

orientation

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default

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false

cellHighlighting

true

Type

Location

Notes

Vivado

<design name>/block_design

<design name>/constraints

<design name>/ip_lib

Vivado Project will be generated by TE Scripts

SDK/HSI

<design name>/sw_lib

Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation

PetaLinux

<design name>/os/petalinux

PetaLinux template with current configuration

Additional Sources

Scroll Title

anchor	Table_ADS
title	Additional design sources

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Type

Location

Notes

SI5338

<design name>/misc/Si5338

SI5338 Project with current PLL Configuration

Prebuilt

Page properties

hidden	true
id	Comments

Notes :

prebuilt files

Template Table:

Scroll Title

anchor	Table_PF
title	Prebuilt files

Scroll Table Layout

orientation

portrait

sortDirection

ASC

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default

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sortEnabled

false

cellHighlighting

true

File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports

---

Report files in different formats

Hardware-Platform-Specification-Files

*.xsa

Exported Vivado Hardware Specification for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Scroll Title

anchor	Table_PF
title	Prebuilt files (only on ZIP with prebult content)

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

File

File-Extension

Description

BIT-File

*.bit

FPGA (PL Part) Configuration File

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Diverse Reports

---

Report files in different formats

Hardware-Platform-Specification-Files

*.xsa

Exported Vivado Hardware Specification for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

HTML
<!-- Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit -->

Reference Design is available on:

TE0841 "Test Board" Reference Design

Design Flow

Page properties

hidden	true
id	Comments

Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Programming

Page properties

hidden	true
id	Comments

Note:

Programming and Startup procedure

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select Create and open delivery binary folder
  Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
optional "TE::pr_program_flash -swapp hello_te0841" possible
Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Connect JTAG and power on PCB
Open Vivado HW Manager
Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"
1. Note SREC Bootloader try to find application on flash, this will stop, if Flash is empty.

Usage

1. Prepare HW like described on section 54395771
2. Connect UART USB (most cases same as JTAG)
3. Power on PCB
  Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
4. Open Serial Console (e.g. putty)
  1. Speed: 9600
  2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Boot process takes a while, please wait.
Image Removed

Linux

Note: Linux boot process is slower on Microblaze.

Open Serial Console (e.g. putty)
1. Speed: 9600
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
1. User Name: root
2. Password: root

Vivado HW Manager:

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
1. Set radix from VIO signals (fm_si...) to unsigned integer.
  Note: Frequency Counter is inaccurate and displayed unit is Hz
2. SI will be configured with MCS firmware, default all off on PCB REV01, PCB REV02 SI5338 will be preconfigured.
3. LED control via VIO
4. MGT CLK Freq can be changed over BUFG_GT control signals divider
5. MCS Reset possible via VIO
6. MIG Reset is possible over VIO
7. MCS can be disabled over VIO (For PCB REV01 MCS is enabled, fpr PCB REV02 MCS is disabled by default VIO)

Scroll Title

anchor	Figure_VHM
title	Vivado Hardware Manager

Image Removed

System Design - Vivado

Page properties

hidden	true
id	Comments

Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title

anchor	Figure_BD
title	Block Design PCB REV02

Image Removed

*Note: REV01 has SI5338 programming default enabled and REV02 default disabled. SI5338 of REV02 is preprogrammed

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Code Block

language	ruby
title	_i_ddr4.xdc
linenumbers	true

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

create_clock -period 4.950 -name ddr4_0_clk -period 4.95 [get_pins */ddr4_0b44/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -period 4.950 -name ddr4_1_clk -period 4.95 [get_pins */ddr4_1b46/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design_adv_inst/CLKIN1]

Code Block

linenumbers

language	ruby
title	_i_qspi.xdc		true

# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7 case analysis
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000


create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay]{6.700 6.700 6.700} [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
#setset_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*][get_pins -hier {*STARTUP*_inst/DTSDO[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier {*STARTUP*_inst/DODTS[*]}] 1.000

Code Block

language	ruby
title	_i_fm.xdc

current_instance msys_i/ddr4_b46/inst
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DTS[*]] 1.000

Code Block

language	ruby
title	_i_fm.xdc
linenumbers	true

property LOC MMCME3_ADV_X0Y2 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]
current_instance -quiet
current_instance msys_i/ddr4_b44/inst
set_property LOC MMCME3_ADV_X0Y0 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]

current_instance -quiet
set_false_path -from [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path]] -fromto [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}] -tosi5338_clk0_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/util_ds_buf_6/U0/USE_BUFG_GT.GEN_OBUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks -of_objectssi5338_clk3_clk_p] -to [get_pinsclocks msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to-of_objects [get_clockspins {msys_i/utilclk_dswiz_buf_50/U0inst/BUFGmmcme3_GT_O[0]}adv_inst/CLKOUT0]]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/clkddr4_wiz_0b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks {-of_objects [get_pins msys_i/utilclk_dswiz_buf_10/U0inst/IBUF_OUT[0]}mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clkddr4_wiz_0b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks {-of_objects [get_pins msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks { -of_objects [get_pins msys_i/utilclk_dswiz_buf_0/U0inst/IBUF_OUT[0]}mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/clkutil_ds_wizbuf_05/inst/mmcme3_adv_inst/CLKOUT0U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks { -of_objects [get_pins msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}ddr4_b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks { -of_objects [get_pins msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}ddr4_b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]

Software Design - Vitis

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Note:

optional chapter separate
sections for different apps

For SDK Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20192021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20192021.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_

fsbl

TE modified 20192021.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_

fsbl_flash

TE modified 20192021.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 20192021.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 20192021.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

scu

MCS Firmware to configure SI5338 and Reset System.

spi_bootloader

TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR.

Here it loads the u-boot.elf from QSPI-

---

General Example:

hello_te0820

Flash to RAM. Hence u-boot.srec becomes redundant.

Descriptions:

Modified Files: bootloader.c
Changes:
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call

hello_te0841

Hello TE0841

Hello TE0820

is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate

Boot.bin.

*.mcs

Software Design - PetaLinux

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Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x6E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xB00000 (kernel)

- - (with this kernel flash address is 0xB00000 (fpga+boot+bootenv) and Kernel size 0xB00000)

U-Boot

Start with petalinux-config -c u-boot

Changes:

No changes.

Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:

Code Block

language	js

#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
 
#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};

Template location: ./sw_lib/sw_apps/

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash (some reinitialisation)

SREC SPI Bootloader

Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code

Changed xilisf_v5_9 to support N25Q512_1V8 for SREC (changes on xilisf.c and xilisf_intelstm.h)

Template location: \sw_lib\sw_apps\srec_spi_bootloader

\sw_lib\sw_services\xilisf_v5_9

xilisf_v5_14

TE modified 2019.2 xilisf_v5_14

Changed default Flash type to 5.

hello_te0841

Hello TE0841 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design - PetaLinux

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Add "No changes." or "Activate: and add List"

PetaLinux KICKstart

Description currently not available.

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x6E0000
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
- (Set kernel flash Address to 0xA00000 and Kernel size to 0xA00000)

U-Boot

Start with petalinux-config -c u-boot

Changes:

No changes.

Change platform-top.h:

Code Block

language	js

Device Tree

Code Block

language	js

Kernel

Start with petalinux-config -c kernel

Changes:

No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

# CONFIG_dropbear is not set
# CONFIG_dropbear-dev is not set
# CONFIG_dropbear-dbg is not set
# CONFIG_packagegroup-core-ssh-dropbear is not set
# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-server-dropbear is not set

Applications

No additional application.

Additional Software

-server-dropbear is not set

Applications

No additional application.

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

"<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

App. A: Change History and Legal Notices

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Document Change History

To get content of older revision got revision go to "Change History" of this page and select older document revision number.

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current-versionmodified-users

Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

current-version

infoType	Current version
dateFormat	yyyy-MM-dd


prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

new document style
21.2 release

2020-05-13

v.8

John Hartfiel

19.2 release

2018-08-07

v.7

John Hartfiel

some notes

2018-06-21

v.5

John Hartfiel

Design update
new assembly variants (PCB REV02

2018-06-21

v.3

John Hartfiel

Release 2017.4

2018-04-16

v.1

Page info

John Hartfiel

created-user

Initial release

---

All

Page info

modified-users

infoType	Modified users
dateFormat	yyyy-MM-dd
type	Flat

---

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 9

New Version Current

Key

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI-Boot mode

SD-Boot mode

JTAG

Usage

Linux

Vivado HW Manager

Vivado HW Manager

System Design - Vivado

Block Design

Constraints

Basic module constraints

Constraints

Basic module constraints

Design specific constraints

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

fsbl

fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

FSBL patch

Kernel

Rootfs

Applications

startup

webfwu

Additional Software

SI5338

SI5345

App. A: Change History and Legal Notices

Document Change History

Legal Notices

Design specific constraints

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch