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| Scroll Title |
|---|
| anchor | Figure_OV_BD |
|---|
| title | TEI0009 Block Diagram |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
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| viewerToolbar | true |
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| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 1517 |
|---|
| diagramName | TEI0009_OV_BD |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 640 |
|---|
|
|
| Scroll Only |
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|
|
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The TEI0009 is integrated with 64 Mbit (8 MByte) Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. Up to 128 MBit (16 MByte) memory is available on other assembly option.
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| Scroll Title |
|---|
| anchor | Table_PWR_PR |
|---|
| title | Module Power Rails |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| tableStyling | confluence |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Connector Designator | VCCIO Schematic Name | Pin | VCC | Direction | Notes |
|---|
| J12 | VIN | 1 | 5 V | In |
| | J3 | 3.3V | 2, 4 | 3.3 V | Out |
| | 5V | 5 | 5 V | Out |
| | J5 | 3.3V | 3 | 3.3 V | Out |
|
|
Bank Voltages
| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | Intel Cyclone 10 LP Bank Voltages |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | Notes |
|---|
| Bank 1...8 | VCCIO1...8 | 3.3V |
|
|
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