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changes.mady.by.user Martin Rohrmüller

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Scroll Title
anchorTable_OBP_DIP
titleDIP-switch SoM configuration settings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SwitchSignal NameONOFFNotes
S1-1---Not connected.
S1-2PROGMODEJTAG enabled for programing mounted SoM's Zynq-SoC.JTAG enabled for programing mounted SoM's SC-CPLD.-
S1-3MODEDrive SoM SC CPLD pin 'MODE' low. (SD-Boot)Leave SoM SC CPLD pin 'MODE' open. (QSPI-Boot)

Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware).

S1-4EN1Drive SoM SC CPLD pin 'EN1' low.Drive SoM SC CPLD pin 'EN1' high.

Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware).

Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM.



Note

Note: Compared to the former revision 02 of this board, the DIP-switch is rotated by 180° due to routing issues.


Scroll Title
anchorFigure_OBP_DIP
titleUser DIP-switch S1

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