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Pin NameModeFunctionDefault Configuration
PGOODOutputPower goodActive high when all on-module power supplies are working properlyPower Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
JTAGENInputJTAG selectLow for normal operation, high for System Controller CPLD access.
EN1InputPower EnableWhen forced low, pulls PORPROG_B low to emulate power on reset.

When forced low, pulls PROG_B low to emulate power on reset.
NOSEQ-No functionNot used.
MODE-No functionNot used.

Note: Pin functionality depends on the running CPLD Firmware, newest one is described here TE0713 CPLD

On-board LEDs

The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design. 


System Controller CPLD (Lattice Semiconductor MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.

By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.

Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.

User can create their own System Controller design using Lattice Diamond software. Once created it can be programmed into CPLD via JTAG interface.CPLD Firmware description:


The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.






Page info

Page info
infoTypeCurrent version

Page info
infoTypeModified users

  • History bugfix
  • Correction of System Controller IO description

v.11John Hartfiel
  • Note USB3

v.9John Hartfiel
  • add default SI5338 clk table

v.8John Hartfiel
  • replace B2B connector section
2017-05-28v.6Jan Kumann
  • Absolute and recommended ratings added.
  • Main components section improved. New top PCB image.
  • Power rails section improved.
  • New physical dimensions images.


Jan Kumann
  • Initial document.