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Functionality of buttons, DIP switches, and LEDs depends on CPLD Firmware. |
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Single +12.0 V power supply is needed to power on the board at power jack J6. Current depends manly on design and cooling solution. Use Intel Power Estimator and/or Your your Intel Quartus Prime Project to estimate min current. Minimum of 3A are recommanded recommended for basic functionality.
DIP-Switches and Push Buttons
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Explain all DIP switches functionality. |
There is a switch (S??) which is connected to RESET signal, it resets the system entirely.are three four-bit dip switches and four buttons, explained in the following:
| Scroll Title |
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| anchor | Table_DIP_PB1 |
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| title | DIP Switches /Push ButtonsSwitche S2 |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Overview 721 | Default | Description | Active Level |
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| S4S2-1 | OFF | SoC PUDC, ON (low - internal FPGA pull ups enabled), OFF (high - internal FPGA pull ups disabled) | | HPS User Switch 1 | L | | S2S4-2 | OFF | N.C. | | HPS User Switch 2 | L | | S2S4-3 | OFF | JTAGEN ON (CPLD access), OFF (FMC access) | FPGA User Switch 1 | L | | S2S4-4 | ON | Enable on board 5V permanently |
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There is no DIPs on TExxxx. In case of TE0790 (XMOD) usage, see DIPs mode.
Jumpers
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Explain all Jumpers functionality and connection. |
| Scroll Title |
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| anchor | Table_DIP_Jumpers2 |
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| title | JumpersDIP Switche S7 (Firmware dependent) |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected to | B2B | Note |
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Boot_R | Open: | | Short: |
LEDs
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Explain all user LEDs functionality and connections. |
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| Overview 21 | Default | Description | Active Level |
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| S7-1 | OFF |
| S7-1 | S7-2 | Boot Selection |
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| 0 | 0 | FPGA | | 1 | 0 | SD/MMC | | 1 | 1 | SPI |
| L | | S7-2 | ON | L | | S7-3 | ON |
| S7-3 | S7-4 | S8-4 | JTAG Selection |
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| X | X | ON | MAX 10 | | ON | ON | OFF | HPS | | ON | OFF | OFF | FPGA | | OFF | ON | OFF | FMC |
| L | | S7-4 | OFF | L |
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| Scroll Title |
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| anchor | Table_DIP_LED3 |
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| title | Carrier LEDsDIP Switche S8 (Firmware dependent) |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Designator| Color | Connected to | B2B | Active Level | Note| Default | Description | Active Level |
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| S8-1 | OFF |
| S8-3 | S8-2 | S8-1 | Output Voltage |
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| ON | ON | ON | 3.3 V | | ON | ON | OFF | 2.5 V | | ON | OFF | ON | 1.8 V | | ON | OFF | OFF | 1.5 V | | OFF | ON | ON | 1.25 V | | OFF | ON | OFF | 1.2 V | | OFF | OFF | ON | 0.8 V (not supported by Intel Cyclone V) | | OFF | OFF | OFF | Selected by HPS (Firmware dependent) |
| L | | S8-2 | OFF | L | | S8-3 | OFF | L | | S8-4 | OFF |
| S7-3 | S7-4 | S8-4 | JTAG Selection |
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| X | X | ON | MAX 10 | | ON | ON | OFF | HPS | | ON | OFF | OFF | FPGA | | OFF | ON | OFF | FMC |
| H |
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| Scroll Title |
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| anchor | Table_LED_ModulePB |
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| title | Module LEDsPush Button (Firmware dependent) |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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DesignatorColorConnected toNote |
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| S1 | OFF | Intel Cyclone V HPS Reset | L | | S3 | OFF | Intel Cyclone V HPS Warm Reset | L | | S4 | OFF | Intel Cyclone V FPGA Reset | L | | S5 | OFF | Intel Cyclone V User Button | L |
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LEDs
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Explain all user LEDs functionality and connections. |
The LED functionality is explained in the following:
| Scroll Title |
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| anchor | Table_LED_Carrier |
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| title | Carrier LEDs (Firmware dependent) |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| J1C | Yellow | Ethernet PHY | L | Ethernet Status | | D25 | Red | Intel MAX 10 | H | Board Status | | D11 | Green | Intel Cyclone V HPS | H | HPS User LED 2 | | D12 | Green | Intel Cyclone V HPS | H | HOS User LED 1 | | D13 | Green | Intel Cyclone V FPGA | H | FPGA User LED 2 | | D14 | Green | Intel Cyclone V FPGA | H | FPGA User LED 1 | | D8 | Green | Intel MAX 10 and Intel Cyclone V | L | Programming Status | | D15 | Green | UART FTDI | L | UART Status | | D18 | Green | UART TX | L | UART TX Status | | D19 | Green | UART RX | L | UART RX Status | | D21 | Green | +12.0V | H | +12.0 V Status | | D1 | Green | +12.0V_FMC | H | +12.0 V FMC Status | | D2 | Green | +5.0V | H | +5.0 V Status | | D3 | Green | +3.3V | H | +3.3 V Status | | D20 | Green | +3.3V_MAX10 | H | +3.3 V Standby Status | | D22 | Green | +3.3V_FMC | H | +3.3 V FMC Status | | D4 | Green | +2.5V | H | +2.5 V Status | | D5 | Green | Intel MAX 10 | H | +1.8 V Status | | D7 | Green | Intel MAX 10 | H | VCC Status | | D9 | Green | Intel MAX 10 | H | VADJ Status | | D6 | Green | Intel MAX 10 | H | FPGA DDR VDD Status | | D23 | Green | Intel MAX 10 | H | HPS DDR VDD Status | | D17 | Green | Intel MAX 10 | H | HPS DDR VTT Status | | D10 | Green | Intel MAX 10 | H | FPGA DDR VTT Status |
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JTAG/UART
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Explain JTAG or UART connection breifly. |
JTAG and UART connections are available through mini USB connectorconnectors.
| Scroll Title |
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| anchor | Table_UART |
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| title | JTAG and UART |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected to | B2B Pin | XMOD Header JB? | Direction | NoteDirection | Note |
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| J13 | Intel MAX 10 via FTDI | IN | JTAG | | J5 | Intel Cyclone V via FTDI | - | UART |
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Reference Designs
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In this Section you must refer to the Reference Design (Test board) for the particular module. For Example: TE0728 Reference Designs |
- TExxxx TEI0022 Reference Designs
Notes
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In this Section you must refer to the Resources Page for the particular module. For Example: TE0728 Resources |