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Type or FileVersion
Vivado Design Suite2019.2
Trenz Project Scripts2019.2.17
Trenz <board_series>_board_files.csv1.4
Trenz apps_list.csv

2.3

Trenz zip_ignore_list.csv1.0
Trenz mod_bd.csv (not included)1.1

...

File NameDescription
Design + Settings
_create_win_setup.cmdUse to create bash files. With 2018.3 and newer also "Module Selection Guide" is included and with 2019.2 prebuilt export for the selected variant
_use_virtual_drive.cmd(Option) Create virtual drive for project execution. See Xilinx AR#52787
design_basic_settings.cmd

Settings for the other *.cmd files. Following Settings are avaliable:

  • General Settings:
    • (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
    • (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project.
    • (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version!
  • Xilinx Setting:
    • XILDIR: Set Xilinx installation path (Default: c:\Xilinx).
    • VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:2019.2). Don't change Vivado Version.
      • Xilinx Software will be searched in:

      • VIVADO (optional for project creation and programming): %XILDIR%\Vivado\%VIVADO_VERSION%\

      • Vitis (optional for software projects and programming): %XILDIR%\Vitis\%VIVADO_VERSION%\

      • LabTools (optional for programming only): %XILDIR%\Vivado_Lab\%VIVADO_VERSION%\

  • Board Setting:
    • PARTNUMBER: Set Board part number of the project which should be created
      • Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)
      • Used for project creation and programming
      • To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design)
      • Example TE0726 Module :
      • USE ID                 |USE PRODID                                   
        PARTNUMBER=1 |PARTNUMBER=te0726-01  
  • Programming Settings(program*file.cmd):
    • SWAPP: Select Software App, which should be configured.
      • Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The *bin,*.mcs or *.bit from this folder will be used.
      • If you will configure the raw *.bit or *.mcs  *.bin  from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="".
      • Example: SWAPP=hello_world   → used the file from prebuilt/boot_image/<partname>/hello_world
                        SWAPP=NA                → used the file from <design_name>/prebuilt/boot_image/<partname>/
    • PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1

      • Attention: it should be only one *.bit, *.msc or *.bin file in the root folder.

design_clear_design_folders.cmd(optional)  Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Project will created.

Hardware Design

vivado_create_project_guimode.cmd

Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process.

Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_create_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_open_existing_project_guimode.cmdOpens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.cmd(optional) Create Vitis project with hardware definition file from prebuild folder. It used the *.xsafrom: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash.cmd(optional)  Programming Flash Memory via JTAG with specified *.bin (Zynq devices) or *.mcs (native FPGA). Used  LabTools Programmer (Vivado or LabTools only. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_binfile.cmdobsolete (optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK  "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_mcsfile.cmdobsolete (optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
program_fpga_bitfile.cmd(optional)  Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
labtools_open_project_guimode.cmd

(optional)  Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

...

NameOptionsDescription (Default Configuration)
TE::help
Display currently available functions. Important: Use only displayed functions and no functions from sub-namespaces 
Hardware Design
TE::hw_blockdesign_create_bd[-bd_name] [-msys_local_mem] [-msys_ecc] [-msys_cache] [-msys_debug_module] [-msys_axi_periph] [-msys_axi_intc] [-msys_clk] [-help]

Create new Block-Design with initial Setting for PS, for predefined bd_names:
fsys→Fabric Only, msys→Microblaze, zsys→7Series Zynq, zusys→UltraScale+ Zynq

Typ TE::hw_blockdesign_create_bd -help for more information

TE::hw_blockdesign_export_tcl[-no_mig_contents] [-no_validate] [-mod_tcl] [-svntxt <arg>]  [-board_part_only] [-help]Export Block Design to project folder <design_name>/block_design/ . Old *bd.tcl will be overwritten!
TE::hw_build_design\[-disable_synth\] \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\]Run Synthese, Implement, and generate Bit-file, optional MCS-file and some report files
Software Design

TE::sw_run_hsi

[-run_only] [-prebuilt_hdf <arg>] [-no_hsi] [-no_bif] [-no_bin] [-no_bitmcs] [-clear] [-help]

obsolete

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/hsi
Run HSI in <design_name>/workspace/hsi for all Programes listed in <design_name>/sw_lib/apps_list.csv
If HSI is finished, BIF-GEN and BIN-Gen are running for these Apps in the prepuilt folders <design_name>/prebuilt/...
You can deactivate different steps with following args :

  • -no_hsi  : *.elf filesgeneration is disabled
  • -no_bif   : *.bif files generation is disabled
  • -no_bin  : *.bin files generation is disabled
  • -no_bitmcs: *.bit and *.mcs file (with software design) is disabled
TE::sw_run_sdk[-open_only] [-update_hdf_only] [-prebuilt_hdf <arg>] [-clear] [-help]

obsolete

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/sdk
Start SDK GUI in this workspace

TE::sw_run_vitis[-all] [-gui_only] [-no_gui] [-workspace_only] [-prebuilt_xsa_only] [-prebuilt_xsa <arg>] [-clear] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_xsa <arg>  or -prebuilt_xsa_only isn't selected.

Copy the XSA File to the working directory:<design_name>/workspace/sdk

Generates Vitis workspace with platform project and start Vitis. Optional parameter

  • -all                     : generate all apps defined in apps_list.csv and export results into the prebuild folder
  • -gui_only            : open only Vitis on the default workspace
  • -no_gui              : Vitis will not opened after project generation
  • -workspace_only : copy XSA file only into the workspace
  • -prebuilt_xsa*     : use prebuit XSA
Programming
TE::pr_init_hardware_manager[-help]Open Hardwaremanager, autoconnect target device and initialise flash memory with configuration from *_board_files.csv.
TE::pr_program_jtag_bitfile[-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_bitfile] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only).
Programming Bitfile from <design_name>/prebuilt/hardware/<board_file_shortname> to the fpga device.
If "-used_basefolder_bitfile" is set, the Bitfile (*.bit)  from the base folder (<design_name>) is used instead of the prebuilts. Attention: Take only one Bitfile in the basefolder!

(MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

TE::pr_program_flash  [-swapp <arg>] [-swapp_av] [-reboot] [-erase] [-setup] [-used_board] [-basefolder] [-help]

Program flash with the given swapp from the prebuilt folder (<design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>).
Available app can be checked with -swapp_av, specify app with -swapp <app_name>
Erase flash only with -erase

TE::pr_program_flash_binfile[-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-force_hw_manager] [-used_basefolder_binfile] [-help]

Attention: For Zynq Systems only!
Program the Bootbin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> to the fpga device.
Appname is selected with: -swapp <app_name>
After programming device reboot from memory will be done.
Default SDK Programmer is used, if not available LabTools Programmer is used.
If "-used_basefolder_binfile" is set, the Binfile (*.bin)  from the base folder (<design_name>) is used instead of the prebuilts. Attention: Take only one Binfile in the basefolder!

TE::pr_program_flash_mcsfile[-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_mcsfile] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only).
Initialise flash memory with configuration from *_board_files.csv
Programming  MCSfile from <design_name>/prebuilt/hardware/<board_file_shortname> to the Flash Device.
After programming device reboot from memory will be done.
If "-used_basefolder_binfile" is set, the MCSfile (*.mcs)  from the base folder (<design_name>) is used instead of  the prebuilts. Attention: Take only one MCSfile in the basefolder!

(MicroBlaze only) If "-swapp" is set, the MCSfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

Utilities
TE::util_zip_project[-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help]

Make a Backup from your Project in <design_name>/backup/

Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported.

TE::util_package_length[-help]Export Package IO length information to *.csv on the doc folder
Beta Test (Advanced usage only!)
TE::ADV::beta_util_sdsoc_project[-check_only] [-help]

Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state.

TE::ADV::beta_hw_remove_board_part[-permanent] [-help]Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported.
TE::ADV::beta_hw_export_rtl_ip\[-help\]Save IPs used on rtl designs as  *.xci in  <design_name>hdl/xci. If sub folder  <board_file_shortname> is defined this will be saved there.
TE::ADV::beta_hw_create_board_part\[-series  <arg>\] \[-all\] \[-preset\] \[-existing_ps\] \[-help\]create PS or preset.xml PS settings from external tcl scripts
TE::ADV::beta_hw_export_binary\[-mode  <arg>\] \[-app  <arg>\] \[-folder   <arg>\] \[-all\] \[-help\]export prebuilt files to an given folder (based from project folder). Special folder is used, if emtpy

...

NameDescriptionValue
IDID to identify the board variant of the module series, used in TE-ScriptsNumber, should be unique in csv list
PRODIDProduct IDProduct Name
PARTNAMEFPGA Part Name, used in Vivado and TE-ScriptsPart Name, which is available in Vivado, ex. xc7z045ffg900-2
BOARDNAMEBoard Part Name, used in Vivado and TE-Scriptsset Board Part Name or "NA", which is available in Vivado, NA is not defined to run without board part and board part ex. trenz.biz:te0782-02-45:part0:1.0
SHORTNAMESubdirectory name, used for multi board projects to get correct sources and save prebuilt dataname to save prebuilt files or search for sources
ZYNQFLASHTYPFlash typ used  for programming Zynq-Devices via SDK-Programming Tools (program_flash)"qspi_single" or "NA", NA is not defined
FPGAFLASHTYPFlash typ used  for programming Devices via Vivado/LabTools

"<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32

Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build.

For Zynq and ZynqMO only Flash name is necessary

PCB_REVSupported PCB Revision"<supported PCB Revision>|<supported PCB Revision>", for ex. "REV02" or "REV03|REV02"
DDR_SIZESize of Module DDRuse GB or MB, for ex. "2GB" or "512MB" or "NA" if not available
FLASH_SIZESize of Module Flashuse MB, for ex. "64MB" or "NA" if not available
EMMC_SIZESize of Module EMMCuse GB or MB, for ex. "4GB" or "NA" if not available
OTHERSOther module relevant changes to distinguish assembly variants
NOTESAdditional Notes
DESIGNSpecify the allowed variants for different designs.see also <design folder>\settings\design_settings.tcl

Block Design Conventions

  • Only one Block-Design per project is supported

  • Recommended BD-Names (currently importend for some TE-Scripts):
     

    NameDescription
    zsysIdendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
    zusysIdendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
    msysIdendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
    fsysIdendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

     

  • Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help

...

See Chapter Board Part Files for more information.

User defined Settings

  • Vivado settings:
    • Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
  • Script settings:
    • Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
  • Design settings:
    • Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/design_settings.tcl". This file will be loaded automatically on script initialisation.
  • ZIP ignore list:
    • Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.
  • SDSOC settings:
    • SDSOC settings will are deposited on the following folder: "<design_name>/settings/sdsoc"

 

User defined TCL Script

TCL Files from "<design_name>/settings/usr" will be load automaticaly on script initialisation.

...