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Table 34: assembly options overview.
To determine the FPGA device, you just read the code on the package under the "Xilinx Spartan" label.
To determine the power supply source, please see paragraph 5.2 Power Supply Sources.
To determine the VcccIO0 voltage, please see paragraph 5.3 On-Board Power Rails.
To determine PCB revision and assembly variant from FPGA, TE0320 have dedicated user signals, which can be read by user core.
Board revision coded in 4 bits REV[3:0]

Table 35: Board revision pins 

To define low (zero) level REV pin connected to ground rail, to define high (one) level REV pin left float (open). These pins should be configured with "pullup" option in user design.
See Table 12 the table below for current list of board revisions.

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Module assembly variant encoded using VAR[5:0] pins.

Table 37: Assembly variants pins
To define low (zero) level VAR pin connected to ground rail through zero resistor, to define high (one) level VAR pin left float (open). These pins should be configured with "pullup" option in user design.
Available module assembly variants listed in Table 38.the table below.

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