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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
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Overview
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Refer to http://trenz.org/te0xyz-info for the current online version of this manual and other available documentation.
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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.
Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.
Key Features
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| John Hartfiel |
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Release Notes and Know Issues
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title | Known Issues |
Requirements
Software
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title | Software |
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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title | Hardware Modules |
*used as reference
Design supports following carriers:
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Carrier Model | Notes | --- |
Additional HW Requirements:
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Requirements
Software
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Additional Hardware | Notes |
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Hardware
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Type | Location | Notes | ||||||||||||||||||||||||||||||
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | ||||||||||||||||||||||||||||||
Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | ||||||||||||||||||||||||||||||
PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
Additional Sources
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title | Additional design sources |
Prebuilt
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Notes :
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title | Prebuilt files |
File
File-Extension
Description
Distro Boot Script file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
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title-alignment | center |
title | Prebuilt files (only on ZIP with prebuilt content) |
File
File-Extension
Description
Distro Boot Script file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note |
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Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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TE::hw_build_design -export_prebuilt |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info |
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"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
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This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for Microblaze
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Generate Programming Files with Vitis
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TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
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TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
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Note: Design contains also Board Part Files for TE0818+TEBF0818 configuration, this board part files are not used for this reference design.
Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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*used as reference |
Content
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Notes :
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For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Notes :
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Notes :
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which did not end with *_tebf0818
Create hardware description file (.xsa file) and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
- Connect JTAG and power on carrier with module
- Set Boot Mode to JTAG
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0818
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
SD-Boot mode
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info Note: See TRM of the Carrier, which is used.
Power On PCB
Expand title boot process 1. Zynq Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads Application into DDR,
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Launch
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Note:
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0820 (optional) |
Note |
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To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this example.
Usage
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
Expand | ||
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1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
hidden | true |
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id | Comments |
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
Open Serial Console (e.g. putty)select COM Port
Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
Code Block | ||||
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petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
You can use Linux shell now.
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i2cdetect -y -r 0 (check I2C 1 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado HW Manager
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Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- Monitoring:
System Design - Vivado
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Block Design
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Image Added |
PS Interfaces
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Activated interfaces:
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SD0 | MIO | |||||||||||||||
SD1 | MIO | |||||||||||||||
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UART0 | MIO | |||||||||||||||
GPIO0 | MIO | SWDT0..1 | TTC0..3 | |||||||||||||
GEM3 | MIO | |||||||||||||||
USB0 | MIO |
Constraints
Basic module constraints
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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Constraints
Basic module constraints
Code Block | ||||
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set_property PACKAGE_PIN K2BITSTREAM.GENERAL.COMPRESS TRUE [get_ports {fclk[0]}]current_design] set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example ---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20212023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20212023.2 xilisf_v5_11 Changed default Flash type to 5.11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- Zynq Example: fsblTE modified 20212023.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20212023.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2021.2 FSBL General:
zynqmp_pmufw
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example:Xilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
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Software Design - PetaLinux
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.bin. |
zynqmp_fsbl
TE modified 2023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
hello_te0818
Hello TE0818 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
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No additional software is needed.
App. A: Change History and Legal Notices
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Note:
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- No changes.
U-Boot
Start with petalinux-config -c u-boot
Changes:
- No changes.
Change platform-top.h:
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Device Tree
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/include/ "system-conf.dtsi"
/ {
};
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FSBL patch
Must be add manually, see template
Kernel
Start with petalinux-config -c kernel
Changes:
- No changes.
Rootfs
Start with petalinux-config -c rootfs
Changes:
- No changes.
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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No additional software is needed.
SI5338
File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
SI5345
File location "<project folder>\misc\Si5345\Si5345-*.slabtimeproj"
General documentation how you work with this project will be available on Si5345
App. A: Change History and Legal Notices
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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Legal Notices
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