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Template Revision 2.1 Design Name always "TE Series Name" + optional CPLD Name + "CPLD" Change List 2.0 to Change List 1.9.1 to
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Overview
CPLD Device with designator U21: LCMX02-256HC
Feature Summary
- JTAG routing
- Boot Mode settings
- LED
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Note:
PCB REV04 REV05 Connection
PCB REV01 REV02 Connection
For PCB REV04 EN1(input) (pulled up in CPLD) / For PCB REV05 REST_EN(output) (Floating in CPLD)
Power Enable from B2B Connector (Positive Enable) (input pin) for PCB revision 04 in this case used only for PGOOD feedback / Reset pin (output pin) for PCB revision 5 in this case this pin is reset pin that is activated by firmware and not by hardware after changing the boot mode via software.
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CPLD Device with designator U46: 10M08SAU169
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For use with the TEBT0865-01 carrier board a small hardware patch on TEBT0865-01 is required. |
Feature Summary
- JTAG_UART
- Power management
- Reset
- I2C
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
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Port Description
Name / opt. VHD Name | Direction | Pin | I/O Bank | Pullup/Down | I/O Standard | Current Strength | Description |
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JTAGEN | in | E5 | -- | 3.3V | fixed to 3.3V | ||
TCK_MAX10 | in | G2 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TMS_MAX10 | in | G1 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TDO_MAX10 | out | F6 | -- | 2.5V (default) | 12mA (default) | JTAG | |
TDI_MAX10 | in | F5 | -- | 2.5V (default) | 12mA (default) | JTAG | |
PG_1V2_PL_DDR | in | H5 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_VCCINT | in | N3 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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LTM_FAULT | in | N2 | 2 | 3.3V LVCMOS | 2mA (default) |
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M_SDA | inout | M3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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EN_SOM | in | K1 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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SC_EXT_3 | in | L2 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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EN_VTT_PL_DDR | out | J2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_2V5_PL_DDR | out | J1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PL_DDR | out | H4 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_PS_AUX | out | M2 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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PG_SOM | out | M1 | 2 | -- | 3.3V LVTTL | 8mA (default) |
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SC_EXT_2 | out | L3 | 2 | -- | 3.3V LVCMOS | 2mA (default) |
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MR | inout | K2 | 2 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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SMB_ALERTn | in | L4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_2V5_PL_DDR | in | L5 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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M_SCL | inout | M4 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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nRST_SYS | out | K5 | 3 | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_PS_DDR | in | M7 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_0V9_GTH_AVCC | in | N6 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_0V9_GTY_AVCC | in | N8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8_PS_GTR_AVTT | in | M9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8 | in | M8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_GTY_AVTT | in | N9 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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M_INT | in | L11 | 3 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_0V85_PS_GTR_AVCC | in | K8 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_2V3 | in | N12 | 3 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_LTM_RUNP | out | M5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V9_GTH_AVCC | out | N5 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V9_GTY_AVCC | out | N4 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_3V3_SW | out | N7 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PS_PLL | out | J6 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_2V5_PS_DDR | out | M13 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_GTY_AVTT | out | N10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_VCC_ADC | out | M11 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_VTT_PS_DDR | out | J8 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8 | out | L10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_GTY_AUX | out | M10 | 3 | -- | 3.3V LVTTL | 8mA (default) |
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PG_3V3_SW | in | J9 | 5 | -- | 3.3V LVCMOS | 2mA (default) |
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PG_1V2_GTH_AVTT | in | H9 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_1V8_AUX | in | G12 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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PG_2V5_PS_DDR | in | L13 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_1V8_PS_GTR_AVTT | out | K10 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_GTH_AUX | out | K11 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V8_AUX | out | K12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_GTH_AVTT | out | J12 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_1V2_PS_DDR | out | J13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_0V85_PS_GTR_AVCC | out | H13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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EN_VCCINT | inout | H8 | 5 | weak pull-up | 3.3V LVCMOS | 2mA (default) |
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EN_2V3 | out | G13 | 5 | -- | 3.3V LVTTL | 8mA (default) |
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Functional Description
JTAG
JTAG access to Intel MAX 10 is available through B2B connector J2.
JTAG Signal | B2B Connector |
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JTAGEN | Pulled Up |
TCK_MAX10 | J2B- D56 |
TDI_MAX10 | J2B- D59 |
TDO_MAX10 | J2B- D58 |
TMS_MAX10 | J2B- D57 |
Power
All power regulators are controlled by the power sequencer core from Intel. It enables and discharges the power regulators and monitors the power good signals. As the power good inputs of the power sequencer are very sensitive, all power good inputs were debounced. https://github.com/intel/multi_power_sequencer
The power-up sequence corresponds to AMD's recommendations and is shown in the table below:
Power Group | Power enable signal (CPLD output signal) | Power good signal (CPLD input signal) | Sequencer Delay1 (PG to next OE) | Qualification Window2 (OE to PG) | Notes |
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0 | -- | EN_SOM | 10µs | 200ms |
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1 | EN_VCCINT | PG_VCCINT |
10µs
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200ms | -- |
EN_2V3 | PG_2V3 | -- | |||
EN_3V3_SW | PG_3V3_SW | +3.3V_SW output signal from U52 | |||
2 | EN_1V8 | PG_1V8 |
10µs
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200ms
| -- |
EN_1V8_AUX | PG_1V8_AUX | -- | |||
EN_1V8_PS_AUX | -- | -- | |||
EN_1V2_PS_PLL | -- | -- | |||
EN_0V9_GTH_AVCC | PG_0V9_GTH_AVCC | -- | |||
EN_0V9_GTY_AVCC | PG_0V9_GTY_AVCC | -- | |||
EN_1V8_VCC_ADC | -- | -- | |||
3 | EN_1V2_PS_DDR | PG_1V2_PS_DDR | 10µs
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200ms | -- |
EN_1V2_PL_DDR | PG_1V2_PL_DDR | -- | |||
EN_2V5_PL_DDR | PG_2V5_PL_DDR | -- | |||
EN_2V5_PS_DDR | PG_2V5_PS_DDR | -- | |||
EN_1V2_GTH_AVTT | PG_1V2_GTH_AVTT | -- | |||
EN_1V2_GTY_AVTT | PG_1V2_GTY_AVTT | -- | |||
4
| EN_VTT_PS_DDR | -- |
10µs
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200ms
| -- |
EN_0V85_PS_GTR_AVCC | PG_0V85_PS_GTR_AVCC | -- | |||
EN_VTT_PL_DDR | -- | -- | |||
EN_1V8_GTH_AUX | -- | -- | |||
EN_1V8_GTY_AUX | -- | -- | |||
5 | EN_1V8_PS_GTR_AVTT | PG_1V8_PS_GTR_AVTT | 10µs | 200ms | -- |
6 | PG_SOM | -- | 0µs | 200ms | -- |
1. Defines the delay from when the master enable is asserted before output enable is asserted, or from when Power Good is asserted until the next rail or group's output enable is asserted.
2. Defines the qualification window for which Power Good must be asserted, after output enable is asserted.
JTAG UART
As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.
The command "nios2-terminal.exe" in the NIOS II command shell is used to output the CPLD Firmware and PCB revision. In case of power problems the power enable and power good signals will be displayed additionally.
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see also https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/jtag-uart-core.html
I2C interface
The CPLD firmware consists of an I2C slave to Avalon MM master bridge Intel FPGA IP, allowing the CPLD registers to be accessed. The device address in the firmware is 0x55, CPLD registers can be accessed via the i2c interface, e.g. in the Linux console with
- i2cget -y 1 0x55 <Index> (for reading) or
- i2cset -y 1 0x55 <Index> <Value> (for writing)
The following table shows the register map for the CPLD interface :
Index | Byte | Register Name | Read/Write | Description | Default |
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0x0 | [7:0] | SC_REVISION | R | CPLD Firmware Revision | 0x3 |
0x1 | [7:0] | PCB_REVISION | R | PCB Revision | 0x2 |
0x6 | [7:0] | pwr_en | R | Status of Power Groups
| 0x7F |
0x8 | [7:0] | power_good_in[7:0] | R | Status of Power Good Signals
| 0xFF |
0x9 | [7:0] | power_good_in[15:8] | R | Status of Power Good Signals
| 0xFF |
0xA | [7:0] | seq_nfault | R | Status of Power Sequencer (Active Low) | 0x1 |
0xE | [7:0] | pwr_usb_ena | R/W | Enables/Disables output signal 'SC_EXT_2'
| 0x0 (0x1 in Reference Design) |
Reference Design
In the reference design, the I2C interface in u-boot is used to read out the CPLD and PCB revision as well as to switch on the output signal 'SC_EXT_2' for the USB voltage on the carrier board TEBT0865. These information will be displayed while booting the reference design as shown:
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Reset
The reset signals ‘MR’ and ‘nRST_SYS’ will be released after power group 6 has been activated.
Appx. A: Change History
Revision Changes
- REV02 to REV03
- changed top design from block design to text design
- added power sequencer
- added debouncing for power good signals
- added jtag_uart
- added i2c interface
- added release for reset (MR and nRST_SYS)
- added logic for SC_EXT_2
- enable/disable USB power for TEBT0865 via I2C
- default: disabled
- update constraining design
- REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | Firmware Release | ||||||||||||||||||||||
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| REV03 | REV02 |
| Update Change History | SC-PGM-TE0865-02_SC0865-03_20240918.zip | ||||||||||||||||||||||
2024-09-18 | v.38 | REV03 | REV02 | Manuela Strücker | Documentation initial |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
Boot Mode
Boot mode can be set either by hardware (dip-switch) on the carrier board or by firmware in linux console or FSBL code. Even after booting boot mode can be changed . After changing the boot mode FPGA is restarted automatically by CPLD, if PCB revision is REV05, otherwise for PCB revision 4 user must reset manually to execute boot mode changing correctly.To change boot mode a state machine continuously monitors the corresponding register that can be change via I2C interface between CPLD and FPGA.
i2cset -y 1 0x20 0x01 0x91
iic_write8(0x20,0x01,0x91)
i2cset -y 1 0x20 0x01 0x93
iic_write8(0x20,0x01,0x93)
i2cset -y 1 0x20 0x01 0x92
iic_write8(0x20,0x01,0x92)
i2cset -y 1 0x20 0x01 0x90
iic_write8(0x20,0x01,0x90)
If PCB revision is REV04, then user must reset manually the carrier board after changing the boot mode using i2cset command in linux console. If PCB revision is REV05, it is not necessary to reset the FPGA by user, because FPGA will be reset automatically via CPLD after changing the boot mode via i2cset command in linux console.
For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.Power
For PCB revision 4 or older PGOOD depends on EN1. There is no additional power management controlled by CPLD. For PCB revision 5 PGOOD depends on PG_ALL signal.
LED
Green LED D2 glows depending on boot mode and whether boot mode is selected by hardware or firmware.
i2cset -y 1 0x20 0x01 0x91 in linux console
i2cset -y 1 0x20 0x01 0x92 in linux console
i2cset -y 1 0x20 0x01 0x93 in linux console
i2cset -y 1 0x20 0x01 0x90 in linux console
Note: asterisk mean one blink. So for example **oooooo mean 2 time blink with a longer break(with the time of 6 blinks)
I2C interface
CPLD firmware consists of a i2c t GPIO block. This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20.In this case related i2c bus is bus 1.
NOSEQ pin
This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:
i2cset -y 1 0x20 0x02 0x01
i2cset -y 1 0x20 0x02 0x00
i2cget -y 1 0x20 0x02
Access to CPLD Registers
CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:
i2cset -y 1 0x20 0x03 <data>
Some of these registers are using to show some information same as CPLD revision and boot mode while booting.
BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).
PUDC is the state of PUDC pin of FPGA.
CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)
BOOT_MODE shows selected boot mode.
If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:
- If boot mode via hardware is selected → Deactive(0)
- If boot mode via software (in linux console or via FSBL code) is selected → Active(1)
- Jed file type can be one of the following types :
- (0) QSPI/SD
- (1) QSPI/JTAG
- (2) JTAG/SD
- (3) default QSPI/JTAG/SD/eMMC
- PUDC can have one of the following state:
- Pull-up activated (0)
- Pull-up deactivated (1)
- The following boot modes can displayed:
- eMMC (0)
- JTAG (1)
- QSPI (2)
- SD Card (3)
The CPLD revision, boot mode and other informations will be displayed while booting as shown:
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If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:
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For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD
Revision Changes
- REV04 to REV05
Adding configuration of boot mode in linux console and via generic parameters
PGOOD pin used as boot mode selector pin.
Adding boot mode configuration via hardware
JTAG time constraint correction
Adding i2c to gpio ip (i2c_slave.vhd)
LED function is changed.
New generic parameter defined : PCB_REV
EN1 pin
is renamed to RST_EN.
pin is input for PCB_REV=4 and it is enable pin same as before.
is reset output for PCB_REV=5 or newer.
- REV03 to REV04
- PCB REV03 support only
X1 is input for USER LED
X0 select X0 or Firmware Blink status to User LE
blink modes for QSPI/SD firmware
- REV02 to REV03
- new Boot Mode variants
- new X0 status blink sequencing
- REV01 to REV02
- Boot Mode variants
- X1
- Remove ERR_STATUS
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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Page info | current-version | current-version | ||||||||||
prefix | v. | REV05 | REV04,REV05 | |||||||||
Page info | modified-user | modified-user |
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2022-10-05 | v.3 | REV05 | REV04,REV05 | Mohsen Chamanbaz |
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2018-08-29 | v.2 | REV04 | REV03 | John Hartfiel |
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v.1 | REV04 | REV03 | John Hartfiel |
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v.1 | REV04 | REV03 | Page info | | created-user | created-user | Initial release||||||
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Appx. B: Legal Notices
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