Page History
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Table of contents
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Overview
CPLD Device with designator U3: LCMX02-256HC
Feature Summary
- Power Management
- FPGA, USB Reset Managment
- JTAG routing
Firmware Revision and supported PCB Revision
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Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Description | |||
|---|---|---|---|---|---|---|
| 3.3V / PG_SENSE | in | 25 | Power Sense | |||
| DONE | in | 28 | FPGA Done Pin | |||
| EN1 | in | 11 | Enable Pin From B2B | |||
| F_TCK | out | 17 | JTAG from/to FPGA | |||
| F_TDI | out | 23 | JTAG from/to FPGA | |||
| F_TDO TDO | in | 9 | JTAG from/to FPGA | |||
| F_TMS | out | 10 | JTAG from/to FPGA | |||
| FPGA_IO1 IO1 | in | 21 | FPGA Pin | |||
| FPGA_IO2 | 20 | / currently_not_used | ||||
| FTDI_RESET_N | out | 5 | USB FTDI Reset | |||
| JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA) | |||
| MODE | in | 13 | / currently_not_used | |||
| NOSEQ | inout | 14 | / currently_not_used | |||
| PG_DDR_PWR PWR | in | 4 | Power Good from DDR | |||
| PGOOD | out | 12 | Power Good to B2B | |||
| PROG_B | out | 27 | FPGA PROG_B | |||
| RESIN | in | 16 | Reset Pin From B2B | |||
| SYSLED1 | out | 8 | LED (Green) | |||
| TCK | in | TCK | 30 | JTAG from/to B2B | ||
| TDI | in | TDI | 32 | JTAG from/to B2B | ||
| TDO | out | 1 | JTAG from/to B2B | |||
| TMS | in | TMS | 29 | JTAG from/to B2B |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).
Power
Power Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
Reset
PROG_B is set to one, if power is good.
FTDI_RESET_N is set to one, if power is good.
LED
| LED | Description |
|---|---|
| SYSLED1 (Green LED D1) | ON when RESIN=0, else FGPIO1 when DONE=1 else Blinking |
Appx. A: Change History
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Revision Changes
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||||||
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| REV01 | REV01 |
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| 2017-03-08 | v.7 | REV01 | REV01 | John Hartfiel | Revision 01 finished | ||||||||||||||||||||||||||
| 2017-03-06 | v.1 | REV01 | REV01 |
| Initial release | ||||||||||||||||||||||||||
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Appx. B: Legal Notices
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