Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Page properties
hiddentrue
idComments

Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board"

DateVersionChangesAuthor
2023-09-132.3
  • update to 22.x
  •  "select COM Port" → Linux command changed
TD
2022-06-152.2
  • add 'QSPI-Boot mode'
  • add 'Get prebuilt boot binaries'
  • changed SD-Boot mode chapter
  •  'Device Tree' chapter expanded
TD
2022-04-212.1
  • update to 21.x
TD
2022-02-282.0
  • add yocto to
    • Overview → Key Features
    • Overview → Requirements
    • Design Flow
    • Launch
  • add section 'Software Design - Yocto'
TD
2021-06-151.2
  • table of content view
  • template history
  • placed a horizontal separation line under each chapter heading
  • replaced <design name> by <project folder>
  • changed title-alignment for tables from left to center
  • update 19.x to 20.x
JH,TD
2020-11-241.1
  • add fix table of content
  • add table size as macro
JH
--1.0----


Custom_table_size_100

Page properties
hiddentrue
idComments

Important General Note:

  • Export PDF to download, if quartus revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Notes :

Refer to http://trenz.org/te0xyztei0050-info for the current online version of this manual and other available documentation.

Key Features

Page properties
hiddentrue
idComments

Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Quartus Prime Pro 21Lite 23.41std
  • Yocto
  • NIOS IIV/m
  • UART
  • ETH
  • USB
  • I2C
  • QSPI flash
  • DDR3 memory
  • User LED

Revision History

Revision History

Page properties
hiddentrue
idComments

Notes :

  • add every update file on the download
  • add design changes on description


Scroll Title
anchorTable_DRH
title-alignmentcenter
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateQuartusProject BuiltAuthorsDescription
2022
2024-
04
08-
21
08
21
23.
4 Pro
1 Lite
TEI0006

TEI0050-test_board_noprebuilt-quartus_

21

23.

4

1std.

0

1-

20220421183824

20240808153710.zip

TEI0006

TEI0050-test_board-quartus_

21

23.

4

1std.

0

1-

20210421183915

20240808153717.zip

Thomas Dück
  • initial release

Release Notes and Know Issues

Page properties
hiddentrue
idComments
Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed
Scroll Title
anchorTable_KI
title-alignmentcenter
titleKnown Issues
Ruoshui Chen
  • updated to  Quartus Lite 23.1std
  • reconstruct pmw and mux code to optimize RTL synthesis
2024-05-1722.1 Lite

TEI0050-test_board_noprebuilt-quartus_22.1std.2-20240517115737.zip

TEI0050-test_board-quartus_22.1std.2-20240517115802.zip

Thomas Dück
  • update to Quartus Lite 22.1std
  • change to Nios V/m
  • TE scripts update
2023-02-1321.1.1 Lite

TEI0050-test_board_noprebuilt-quartus_21.1.1-20230213145533.zip

TEI0050-test_board-quartus_21.1.1-20230213145613.zip

Thomas Dück
  • fixed BSP_DIR in software project
2022-08-1121.1.1 Lite

TEI0050-test_board_noprebuilt-quartus_21.1.1-20220811093744.zip

TEI0050-test_board-quartus_21.1.1-20220811093807.zip

Thomas Dück
  • initial release


Release Notes and Know Issues

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueIssuesDescriptionWorkaroundTo be fixed versionNo known issues---------

Requirements

Software

Page properties
hiddentrue
idComments
Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixedlist of software which was used to generate the design


Scroll Title
anchorTable_SWKI
title-alignmentcenter
titleSoftwareKnown Issues

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Software
Issues
Version
Description
Note
Quartus Prime Pro21.4needed
NIOS II SBT for Eclipse---optional
Yoctodunfelloptional (more information: Yocto KICKstart#Used source files)
SI ClockBuilder Pro
WorkaroundTo be fixed version
No known issues---------
optional


Requirements

Hardware

Software

Page properties
hiddentrue
idComments

Notes :

  • list of hardware software which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:


*used as reference

Scroll Title
anchorTable_SW
title
Scroll Title
anchorTable_HWM
title-alignmentcenter
titleHardware ModulesSoftware

Scroll Table Layout
widths
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstyle
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Module ModelBoard Part Short NameYocto Machine NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes

Design supports following carriers:

Scroll Title
anchorTable_HWC
title-alignmentcenter
titleHardware Carrier
SoftwareVersionNote
Quartus Prime Lite23.1stdNios V license is needed. For more information see: Intel Nios V Processors
RiscFree IDE for Intel FPGAs23.1stdneeded


Hardware

Page properties
hiddentrue
idComments

Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
anchorTable_HWM
title-alignmentcenter
titleHardware Modules
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueCarrier ModelNotes---

*used as reference

Additional HW Requirements:

*used as reference

Scroll Title
anchorTable_AHW
title-alignmentcenter
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
USB cable for JTAG/UARTCheck Carrier Board and Programmer for correct type

Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Intel devices

Design Sources

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TEI0050-01-AAH11AAH11REV018MByte2MByte----
TEI0050-01-AAH13A*AH13REV018MByte8MByte----

*used as reference

Design supports following carriers:

Location
Scroll Title
anchorTable_HWC
title-alignmentcenter
titleHardware Carrier
Scroll Title
anchorTable_DS
title-alignmentcenter
titleDesign sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Type
Carrier ModelNotes
Quartus

<project folder>/source_files/quartus

<project folder>/source_files/<Board Part Short Name>/quartus

Quartus project will be generated by TE Scripts

(Optional) Source files for specific assembly variants

Software

<project folder>/source_files/software

<project folder>/source_files/<Board Part Short Name>/software

Additional software will be generated by TE Scripts

(Optional) Source files for specific assembly variants

Yocto<project folder>/source_files/os/yoctoYocto BSP layer template for linux

Prebuilt

---

*used as reference

Additional HW Requirements:

Scroll Title
anchorTable_AHW
title-alignmentcenter
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
USB cable for JTAG/UARTCheck Carrier Board and Programmer for correct type

*used as reference

Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Intel devices

Design Sources

Scroll Title
anchorTable_DS
title-alignmentcenter
titleDesign sources
Page properties
hiddentrue
idComments

Notes :

  • prebuilt files
  • Template Table:
    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidthssortByColumn
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn

    1
    sortEnabledfalse
    cellHighlightingtrue

    File
    Type
    File-Extension
    Location
    Description
    Notes
    SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardwareSRAM Object File*.sofRam configuration fileProgrammer Object File*.pofFPGA configuration fileJTAG Indirect Configuration file*.jicFlash configuration fileRaw binary file*.rbfFPGA configuration fileDiverse Reports---Report files in different formatsSoftware-Application-File*.elfSoftware application for NIOS II processor system

    Device Tree

    *.dtbDevice tree blobSFP-File*.sfpBoot image with SPL (Secondary Program Loader)BIN-File*.binImage with linux kernel and ram diskCONF-File*.confBoot configuration file (extlinux.conf)Yocto linux image*.wicLinux image for SD card Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

    File

    File-Extension

    Description

    SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardwareSRAM Object File*.sofRam configuration fileJTAG indirect configuration file*.jicFlash configuration fileRaw binary file*.rbfFPGA configuration fileDiverse Reports---Report files in different formatsSoftware-Application-File*.elfSoftware application for NIOS II processor system

    Download

    Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

    Page properties
    hiddentrue
    idComments

    Reference Design is available on:

    Design Flow

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue
    Page properties
    hiddentrue
    idComments
    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

    TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality

  • Open create_project_win.cmd/create_project_linux.sh:
    Image Removed
  • Select Board in "Board selection"
  • Click on "Create project" button to create project
    1. (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
  • Create and configure your Yocto Linux project, see Yocto KICKstart
  • Copy the generated meta-<module> folder from <project name>/os/yocto/meta-<module> to the path/to/yocto/poky/ directory
  • Follow the steps from Yocto KICKstart#Create a project for an Intel FPGA device without running the 'bitbake' command
  • Add the generated bsp layer meta-<machine> to path/to/yocto/poky/build/conf/bblayers.conf with:

    Code Block
    themeMidnight
    linenumberstrue
    bitbake-layers add-layer ../meta-<module>
    Info

    Note: The generated meta-<module> layer depends on the meta-altera layer (for more information see: Yocto KICKstart#Used source files), so you need to add both bsp layers to bblayers.conf

    Redefine the variable MACHINE with '<module>-<Board-Part-Short-Name>' in path/to//yocto/poky/build/conf/local.conf. The correct MACHINE name can be found in the #Hardware table.
    Also define the variables INITRAMFS_IMAGE_BUNDLE and INITRAMFS_IMAGE to generate a ram disk image.

    Code Block
    themeMidnight
    linenumberstrue
    sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf
    echo -e '\nMACHINE = "<module>-<Board-Part-Short-Name>"' >> conf/local.conf
    echo -e '\nINITRAMFS_IMAGE_BUNDLE = "1"' >> conf/local.conf
    echo -e 'INITRAMFS_IMAGE = "te-initramfs"' >> conf/local.conf

    Build the image with following command (the image recipes are located in meta-<module>/recipes-core/images/):

    Code Block
    themeMidnight
    linenumberstrue
    bitbake te-image-minimal

    Launch

    Scroll Ignore
    Page properties
    hiddentrue
    idComments

    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Get prebuilt boot binaries

    Note

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    1. Run create_project_win.cmd/create_project_linux.sh
    2. Select Module in 'Board selection'
    3. Click on 'Export prebuilt files' button
      1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

    SD-Boot mode

    Prepare SD card as follows for SD-Boot

    Run following command to get the device name of the SD card  (e.g. /dev/sdx):

    Code Block
    themeMidnight
    linenumberstrue
    lsblk
    Insert SD card in the SD card reader, unmount and erase it
    Code Block
    themeMidnight
    linenumberstrue
    sudo umount /dev/sdx
    sudo sfdisk --delete /dev/sdx

    Create required partitions on the SD card (partition 1: 50MB, FAT32 / partition 2: 2MB, a2) 

    Code Block
    themeMidnight
    linenumberstrue
    echo -e ',50M,c\n,2M,a2' | sudo sfdisk /dev/sdb --force
    sudo mkfs.vfat -F 32 -n boot /dev/sdb1

    Copy the u-boot file to partition 2 of the SD card

    Code Block
    themeMidnight
    linenumberstrue
    sudo dd if=path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp of=/dev/sdb2 bs=1M seek=0
    sync
    
  • Copy  zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/  via file manager to the partition 1 (named 'boot')  on SD card
  • Set Boot Mode to SD-Boot
    • Depends on Carrier, see carrier TRM
  • Insert SD-Card in the SD-Slot
  • QSPI-Boot mode

    Option for u-boot-with-spl.sfp on QSPI flash and zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and extlinux/extlinux.conf on SD card.

    Use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: #Get prebuilt boot binaries

  • Connect JTAG and power on carrier with module
  • Open path/to/intelFPGA_lite/21.1/embedded/Embedded_Command_Shell.bat ( Win OS)/path/to/intelFPGA_lite/21.1/embedded/embedded_command_shell.sh (Linux OS) from Intel SoC FPGA EDS
  • Run following commands:

    Code Block
    themeMidnight
    linenumberstrue
    quartus_hps -c 1 -o pv -a 0x0 path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp
  • Copy  zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ to SD card.
  • Set Boot Mode to QSPI-Boot
    • Depends on Carrier, see carrier TRM
  • Insert the SD card in the SD-Slot
  • QSPI

    1. Connect JTAG and power on carrier with module
    2. Open create_project_win.cmd/create_project_linux.sh
    3. Select correct board in "Board selection"
    4. Click on "Program device" button
      1. if prebuilt files are available: select "Program prebuilt file"
      2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
      3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
    5. Click on "Start program device" button

    JTAG

    Not used on this example.

    Usage

    1. Prepare HW like described on section Kopie von _template_TEI0000 Intel Reference Design (Access rights for internal use only)
    2. Connect UART USB (most cases same as JTAG)
    3. Connect your board to the network
    4. Power on PCB

    UART

    Open Serial Console (e.g. PuTTY)

    select COM Port

    Info

    Win OS: see device manager

    Linux OS: see  dmesg | grep tty  (UART is *USB1)

  • Speed: 115200
  • Press reset button
  • Console output depends on used Software project, see Software Design - SDK#Application
  • Linux Console:

    Login data:

    Info

    Note: Wait until Linux boot finished

    Code Block
    themeMidnight
    linenumberstrue
    Username: root
    Password: root

    You can use Linux shell now.

    Code Block
    themeMidnight
    linenumberstrue
    i2cdetect -y -r 1   (check I2C 1 Bus)
    dmesg | grep rtc    (RTC check)
    udhcpc              (ETH0 check)
    lsusb               (USB check)
    Quartus

    <project folder>/source_files/quartus

    Quartus project will be generated by TE Scripts

    Software

    <project folder>/source_files/software

    Additional software will be generated by TE Scripts


    Prebuilt

    Page properties
    hiddentrue
    idComments

    Notes :

    • prebuilt files
    • Template Table:

      • Scroll Title
        anchorTable_PF
        title-alignmentcenter
        titlePrebuilt files (only on ZIP with prebult content)

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        File

        File-Extension

        Description

        SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
        SRAM Object File*.sofRam configuration file
        Programmer Object File*.pofFPGA configuration file
        JTAG Indirect Configuration file*.jicFlash configuration file
        Raw binary file*.rbfFPGA configuration file
        Diverse Reports---Report files in different formats
        Software-Application-File*.elfSoftware application for NIOS II processor system

        Device Tree

        *.dtbDevice tree blob
        SFP-File*.sfpBoot image with SPL (Secondary Program Loader)
        BIN-File*.binImage with linux kernel and ram disk
        CONF-File*.confBoot configuration file (extlinux.conf)
        Yocto linux image*.wicLinux image for SD card




    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
    SRAM Object File*.sofRam configuration file
    JTAG indirect configuration file*.jicFlash configuration file
    Diverse Reports---Report files in different formats
    Software Application File*.elfSoftware application for Nios V processor system


    Download

    Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

    Page properties
    hiddentrue
    idComments

    Reference Design is available on:

    Design Flow

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments
    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

    See also:


    The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

    TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality

    1. Open create_project_win.cmd/create_project_linux.sh:
      Image Added
    2. Select Board in "Board selection"
    3. Click on "Create project" button to create project
      1. (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"

    Launch

    Scroll Ignore


    Page properties
    hiddentrue
    idComments

    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Get prebuilt files

    Note

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    1. Run create_project_win.cmd/create_project_linux.sh
    2. Select Module in 'Board selection'
    3. Click on 'Export prebuilt files' button
      1. Folder <project folder>/_binaries_<Article Name> with subfolder programming_files will be generated and opened

    QSPI

    1. Connect JTAG and power on carrier with module
    2. Open create_project_win.cmd/create_project_linux.sh
    3. Select correct board in "Board selection"
    4. Click on "Program device" button
      1. if prebuilt files are available: select "Program prebuilt file"
      2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
      3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
    5. Click on "Start program device" button

    JTAG

    Not used on this example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)

    UART

    1. Open Serial Console (e.g. PuTTY)
      1. select COM Port

        Info

        Win OS: see device manager

        Linux OS: see ls -l dev/serial/by-id  (UART is *USB1)


      2. Speed: 115200
    2. Press reset button S1
    3. Press user button S2 to toggle between different LED sequences
    4. Console output depends on used Software project, see Software Design - SDK#Application

    System Design - Quartus

    Scroll Ignore


    Page properties
    hiddentrue
    idComments

    Note:

    • Description of Block Design - Project, Block Design - Platform Designer, ... Block Design Pictures from Export...

    Block Design

    The block designs may differ depending on the assembly variant.

    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design - Project


    Image Added


    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design - Platform Desginer



    Image Added

    Software Design - SDK

    Scroll Ignore


    Page properties
    hiddentrue
    idComments
    Note:
    • optional chapter separate

    • sections for different apps

    Application

    Page properties
    hiddentrue
    idComments

    ----------------------------------------------------------

    General Example:

    hello_tei0006

    Hello TEI0006 is a Hello World example as endless loop instead of one console output.

    Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

    test_tei0050

    'test_tei0050' prints the current mode of the LEDs in console.

  • ...
  • System Design - Quartus

    Scroll Ignore
    Page properties
    hiddentrue
    idComments

    Note:

    • Description of Block Design - Project, Block Design - Platform Designer, ... Block Design Pictures from Export...

    Block Design

    The block designs may differ depending on the assembly variant.

    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design - Project
    >>Project<<
    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design - Platform Desginer
    >>Platform Designer<<

    HPS Interfaces

    Activated interfaces:

    TypeNoteDDR--EMAC0--EMAC1--GPIO0--GPIO1--GPIO2--I2C0--I2C1--QSPI--SDMMC--UART0--UART1--USB0--USB1--CAN0--CAN1--

    Software Design - SDK

    Scroll Ignore
    Page properties
    hiddentrue
    idComments
    Note:
    • optional chapter separate

    • sections for different apps

    Application

    Page properties
    hiddentrue
    idComments

    ----------------------------------------------------------

    General Example:

    hello_tei0006

    Hello TEI0006 is a Hello World example as endless loop instead of one console output.

    Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

    ...

    Software Design - Yocto

    Scroll Ignore

    For Yocto installation and project creation, follow instructions from:

    U-Boot

    Start with Create a custom BSP layer for Intel SoC or FPGA#Configure u-boot

    File location: meta-<module>/recipes-bsp/u-boot/

    Changes:

    • No changes

    Device Tree

    U-boot Device Tree

    Code Block
    languagejs
    titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-bsp/u-boot/files/<module_series>_<Board_Part_Short_Name>/dts/<module_series>_<Board_Part_Short_Name>.dts
    #u-boot device_tree.dts
    / {
    };
    
    Code Block
    languagejs
    titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-bsp/u-boot/files/<module_series>_<Board_Part_Short_Name>/dts/<module_series>_<Board_Part_Short_Name>-u-boot.dts
    #device_tree-u-boot.dts
    / {
    };
    

    Kernel Device Tree

    Code Block
    languagejs
    titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-kernel/linux/files/dts/<module_series>_<Board_Part_Short_Name>.dts
    #kernel device_tree.dts
    / {
    };
    

    Kernel

    Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernel

    File location: meta-<module>/recipes-kernel/linux/

    Changes:

    • No changes.

    Images

    Image recipe for minimal console image

    File location: meta-<module>/recipes-images/yocto/

    Image recipes:

    • te-image-minimal.bb: create minimal linux image
    • te-initramfs.bb: required for building an image with initial RAM Filesystem

    Added packages/recipes:

    • No packages/recipes

    Rootfs

    Used filesystem: Initial RAM Filesystem (initramfs)

    Appx. A: Change History and Legal Notices

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Document Change History

    To get content of older revision  got to "Change History"  of this page and select older document revision number.

    Page properties
    hiddentrue
    idComments
    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following
      • Add new row below first

      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports


    Scroll Title
    anchorTable_dch
    title-alignmentcenter
    titleDocument change history

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths2*,*,3*,4*
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    change list
    DateDocument Revision

    Authors

    Description

    Page info
    modified-date
    modified-date
    dateFormatyyyy-MM-ddMM-dd

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    Modified by
    typeFlat

    • update to Quartus Prime Lite 23.1
    2024-05-17


    v.7


    Thomas Dück


    • update to Quartus Prime Lite 22.1
    • document style update
    2023-02-14v.6Thomas Dück
    • fixed BSP_DIR in software project
    2022-08-11v.5Thomas Dück
    • inital release
    --all

    Page info
    infoTypeModified users
    dateFormatyyyy-MM-dd
    typeFlat

    --


    Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices





    scroll-pdf-ignore


    Custom_fix_page_content

    Table of contents

    Table of Contents
    outlinetrue

    scroll-only


    HTML
    <style>
    .wiki-content .columnLayout .cell.aside {
    width: 0%;
    }</style>
    
    Scroll pdf ignore
    true
    Custom_fix_page_content

    Table of contents

    Table of Contents
    outline