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More reading, this time Ethernet Lite user guide. If packets are on MII bus, and if they are at all valid (even if FCS is missing etc) then at least some bytes should be visible in the RX ping-pong buffers, right?

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The Block Diagram of the System is bit more complicated as it should be: the CLKOUT block is small IP Core that sends a global clock to IO buffer with no phase delay , that is uses DDR IO using DDR I/O FlipFlop. This clock has exactly same phase as the TXD outputs to PHY. This output was only used for measurements, it is not wired to the PHY ref clock at all.

Clocking is also too complicated, during debugging I derived the PHY clock from System Clock, and System Clock from MGT Clock. Of course there was no need for this...