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Custom_table_size_100

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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.2
  • Changes Xilinx to AMD
ED

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Periphery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

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Notes :

The Trenz Electronic TEB2000 carrier board provides functionality for development, evaluation and testing purposes of Trenz 4 x 5 cm SoMs (System on Module).

The carrier board is equipped with a broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.

See page "4 x 5 SoM Carriers" for more information about the SoM's supported by the TE0703 TEB2000 Carrier Board.

Refer to http://trenz.org/teb2000-info (Links is correct, url should be redirect to Resources Page, but is not) for the latest online version of this manual and other available documentation.

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examplesexamples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • On Board:
    • System Controller (SC) (LCMXO2-1200HC-4TG144I1))
    • Mini USB for JTAG and UART connection (FTDI FT2232H), compatible with AMD and other vendor development tools
    • Mini USB second UART connection (FTDI FT230XQ)
    • SDIO port expander
    • 4 x User LEDs
      • D1 and , D2 are connected to the SC, their function depends on the firmwareSC (firmware-dependent functionality)
      • D3, D4 connected to SC and D3 and D4 are connected to the SC and the 4 x 5 SoM and can be directly controlled by it
    • 2 x User push button
      • Connected to the SC , the fuction is firmware depend(firmware-dependent functionality)
      • Currently used for Hard- and Soft-Reset
    • 4 User DIP switches
      • Enable/disable update of the SC
      • MIO0 (readable accessible signal by SC and SoM)
      • 2 "mode" bits
  • Interface:
    • Trenz 4 x 5 SoM socket
      • 3 x Samtec LSHM series high-speed connectors
    • Micro SD card connector
    • 2 x VG96 backplane connectors assembly option (mounting holes and solder pads)
    • Mini or Normal USB for SoM USB-OTG connection 1)
    • RJ45 GbE connector
  • Power:
    • Overvoltage-, undervoltage- and reversed- supply-voltage-protection
    • Barrel jack (2.1 mm) for 5V power supply input
  • Dimension:
    • 100 mm x 64.5 mm
  • Notes

1)Depends on assembly variant

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

SD Interrupt → SD Detect



scrollscroll-title
anchorFigure_OV_BD
title-alignmentcenter
titleTExxxx TEB2000 block diagram


Scroll Ignore

draw.io Diagram
bordertrue
diagramNameTEB2000_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth630
revision1113


Scroll Only


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .


Scroll Title
anchorFigure_OV_MC
title-alignmentcenter
titleTExxxx TEB2000 main components


Scroll Ignore
draw.io Diagram
bordertrue
diagramNameTEB2000-01_Figure_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth
642
641
revision
3
4


Scroll Only


  1. System Controller (SC) CPLD, U5
  2. USB-to-JTAG/UART-FTDI, U4
  3. USB-to-UART-FTDI, U12
  4. UART LEVEL Level Shifter, U8
  5. SDIO Port Expander, U2
  6. I²C Repeater, U7
  7. Power Input Protection, U11
  8. DCDC, U3
  9. USB Power Supply Switch, U1
  10. Reset / Push button, S1, S6
  11. 4x Dip SwitchesSwitch, S2
  12. ULED1 LED D1 (red), D2 (green)
  13. FLED1 con to SC PL9A, LED D3 (red), D4 (green)
  14. Ethernet jackJack, J14
  15. Samtec Razor Beam™ LSHM-150/130 B2B connector, JB1, JB2, JB3
  16. Footprint Assembly option for VG96 Connector / VG96 Connector, J1, J2
  17. +5V power jackPower Jack, J13
  18. microSD Card Socket, J3
  19. Bank IO Voltages jumper, J5, J8, J9, J10
  20. Mini USB Type B jackJack, J4 (FT2232H), J21 (FT230XQ)
  21. USB Host Connector, either a J6 (USB A jack, J6  or a ) or J12 (Micro USB, J12)

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
anchorTable_OV_IDS
title-alignmentcenter
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

EEPROMPreprogrammed with AMD Microchip programmer license

Do not overwrite!

System Controller CPLDPreprogrammed
with SC CPLD Firmware		The Visit TEB2000 Firmware sources are available for modification to your needs.
Visit TE0703 Firmware for further information.

The carrier is shipped in the following configuration:

  • VCCIO -A/B/C/D voltage selection jumpers are all set to 1.8 V.
  • SD IO Voltage jumper J11 is set to 1.8 V.
  • VBat jumper J7 is set to gnd.
  • Switch S1 configured as reset button in CPLD.
  • The Base Board is shipped with two VG96 backplane connectors, which are not soldered.
    • for further information.

    Signals, Interfaces and Pins

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    For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

    Note
    • Table with all connectors and Designator
    • List of different interfaces per connector
    • IO CNT (for FPGA IOs where functionality can be changed by customer)


    Connectors

    Scroll Title
    anchorTable_SIP_C
    title-alignmentcenter
    titleBoard Connectors

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Connector TypeDesignator

    		InterfaceIO CNTNotes
    VG96J1JB1 - IO

    48 SE / 24 DIFF


    VG96J1JB3 - IO36 SE / 18 DIFF
    VG96J1B2B/SC - I²C2

    Micro USB Type A/B 1)

    		J12JB3 - USB 2.0 OTG2
    RJ-45 Ethernet
    		J14B2B - ETH8
    RJ-45 EthernetJ14SC - ETH LED4
    VG96J2JB2 - IO65 SE / 32 DIFF
    VG96J2SC - IO16
    Mini USB Type BJ21SC - USB 2.02
    microSD Card socketJ3SDIOSDIO 2)
    Mini USB Type BJ4FTDI - USB 2.02
    USB Type A 1)J6JB3 - USB 2.0 OTG2
    B2B
    		JB1
    		J1 -
    S2 DIP switches are configured as follows:
    SwitchPositionSignal nameDescriptionS2-1OFFCM1

    PGOOD signal active state set to high.

    S2-2ONCM0

    FPGA access to SoM.

    See TE0703 Firmware section "JTAG" for access options.

    S2-3

    ONJTAGENS2-4ONMIO0Boot source set to SD Card.
    See TE0703 Firmware section "Boot Mode" for access options.

    Signals, Interfaces and Pins

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    For subsection examples see: <Series Name> TRM Template section examples

    Note
    • Table with all connectors and Designator
    • List of different interfaces per connector
    • IO CNT (for FPGA IOs where functionality can be changed by customer)

    Connectors

    Designator
    Scroll Title
    anchorTable_SIP_C
    title-alignmentcenter
    titleBoard Connectors

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    		Connector TypeConnectionEndpointInterfaceIO CNTNotes
    VG96J1JB1IO

    48 SE / 24 DIFF

    		To SoM via JB1
    3x 2.54 mm Pin HeaderJ7JB1Battery Voltage1To SoM via JB1.
    1.2 to 1.5 Volt
    RJ-45 Ethernet
    		J14JB1Ethernet8Gbit capable, Phy MDI to SoM, LEDs  to SC
    VG96J2JB2
    IO
    		48 SE / 24 DIFF
    To SoM via JB2VG96J2JB2IO18 SE / 9 DIFFTo SoM via JB2VG96J1JB3IO36 SE / 18 DIFFTo SoM via JB3Micro USB
    Type A/B
    or
    USB Type AExclusive J6 or J12JB3USB 2.0 OTG3To SoM, Data ± and ID. Only on USB jack possibleVG96J2SCIO18To SC X0 unto X17

    B2B
    		JB1
    		2 x UART or 4 x IO
    		4

    B2BJB1I2C or 2 x IO
    		2
    B2BJB1SC - IO2
    B2BJB1SDIOSDIO 2) or 6 x IO
    B2BJB1ETH  - MDIETH
    B2BJB2J2 - IO65 SE / 32 DIFF
    B2BJB2SC
    - JTAG4
    To SC

    B2BJB2SC
    - Reset
    , RESIN
    1
    To SCMini USB Type BJ4SCUSB 2.02To Carrier FTDIMini USB Type BJ21SCUSB 2.02To Carrier FTDIB2BJB1SCUART2UART to SoM for application
    B2BJB1SCUART2UART to SoM for HSS/System Boot 
    microSD Card socketJ3SC or SoMSD6VG96J1SoM and SCI²C2To SoM via JB1and SC

    Test Points


    B2BJB22 x LED or 2 x IO2
    B2BJB3J1 - IO36 SE / 18 DIFF
    B2BJB3USBUSB

    1) Depending on the variant only one of the USB connectors is assembled.
    2) Depending on firmware microSD Card socket is connected to SC or SoM. Refer to TEB2000 CPLD Firmware for further information.


    Test Points

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    you

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    you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

    Example:

    Test PointSignalNotes1)
    TP1PWR_PL_OK

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.


    Scroll Title
    anchorTable_SIP_TPs
    title-alignmentcenter
    titleTest Points Information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Test PointSignal
    Direction 1)
    Notes
    TP15VIN
    		INCarrier supply voltage

    TP25VIN
    INCarrier supply voltage

    TP3VIN
    INCarrier supply voltage after protection circuit

    TP4VIN
    INCarrier supply voltage after protection circuit

    TP53.3V
    OUT
    Carrier generated

    TP63.3V
    OUTCarrier generated

    TP7VCCIOA
    INIO Voltage, generted by SoM

    TP8VCCIOA
    INIO Voltage, generted by SoMTP9VCCIOBINIO Voltage, generted by SoMTP10VCCIOBINIO Voltage, generted by SoMTP11VCCIOCINIO Voltage, generted by SoMTP12VCCIOCIN

    TP9VCCIOB
    TP10VCCIOB
    TP11VCCIOC
    TP12VCCIOC
    IO Voltage, generted by SoM

    TP13VCCIOD
    INIO Voltage, generted by SoM

    TP14VCCIOD
    INIO Voltage, generted by SoM

    TP15M1.8VOUT
    IN
    IO Voltage, generted by SoM

    TP16M1.8VOUT
    INIO Voltage, generted by SoM

    TP17M3.3VOUT
    INIO Voltage, generted by SoM

    TP18M3.3VOUT
    INIO Voltage, generted by SoMTP19UART_VBUSINCarrier USB Bus Voltage

    TP19UART_VBUS
    TP20UART_VBUS
    INCarrier USB Bus Voltage

    TP21VCCJTAG
    INJTAG Reference Voltage generated, by the SoM

    TP22VCCJTAG
    IN
    JTAG Reference Voltage generated, by the SoM

    TP233.3V_SD
    OUT
    Carrier microSD card Voltage

    TP243.3V_SD
    OUTCarrier microSD card Voltage

    TP25USB-VBUS_R
    OUTCarrier USB Bus Voltage

    TP26USB-VBUS_R
    OUT
    Carrier USB Bus Voltage

    TP27ETH-VCC
    IN

    TP28ETH-VCC
    IN

    TP29Vbus
    INExternal/FTDI USB Bus Voltage

    TP30Vbus
    INExternal/FTDI USB Bus Voltage

    TP31CM1
    INDIP Switches

    TP32CM0
    IN

    TP33MIO0
    IN

    TP34JTAGEN
    IN

    1) Direction:

    IN: Input from the point of view of this board.
  • OUT: Output from the point of view of this board.


    • On-board Peripherals

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    Notes :

    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

    Example:

    Chip/InterfaceDesignatorConnected ToNotes
    ETH PHYU10
    • B2B connector J1
    • SoC MIO
    		Gigabit ETH PHY



    Preprogrammed with AMD programmer license.
    Scroll Title
    anchorTable_OBP
    title-alignmentcenter
    titleOn board peripherals

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Chip/InterfaceDesignatorConnected ToNotes

    System Controller

    		U5
    SoM
    • B2B Connector
    • FTDI
  • JB1 B2B connector
    UART, 6x MIO, 5x Config signals
  • JB2 B2B connector
    JTAG, RESIN and 18 IOs
    • (FT2232H) U4
    • FTDI (FT230XQ) U12
    • SD Port Expander

    Channel B1, Channel Select, SD Interrupt
    • U2
    • Push button S1
    • DIP Switch S2
    • All LEDs
    The Firmware sources are available for modification to your needs.
    		Visit TEB2000 CPLD Firmware for further information.

    FTDI FT2232H

    		U4
    • SC
    • J4
    		JTAG/UART for Application

    EEPROM

    		U10
    • FTDI

    Do not overwrite!

    FTDI FT230XQ

    		U12
    • SC
    • J21

    UART for HSS/System Boot

    Oscillator

    EEPROM

    U6
    U10
    U4
    • FTDI
    12 MHz

    Preprogrammed with Microchip programmer license.

    Do not overwrite!

    SD IO Port Expander

    		U2
    • SC
    Via JB1 B2B connector to SoM
    • B2B Connector JB1
    • microSD Card J3

    I2C Repeater

    		U7
    • VG96 J1
    • B2B JB1
    • SC U5

    Oscillator

    		U6
    • FTDI U4

    12 MHz



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    For example subsections

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    For example subsections see: <Series Name> TRM Template section examplesexamples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

    Configuration and System Control Signals

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    • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
    • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)


    Endpoint
    Scroll Title
    anchorTable_OV_CNTRL
    title-alignmentcenter
    titleController signal.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Physical defined Signals

    Signal Name

    Connector.Pin

    Signal Name

    		Direction1)Description
    S1S1.2 / S1.4
    S1SC.BANK-0.114
    IN
    Reset push

    Push button

    .

    Functions are firmware dependant.
    Visit TE0703 CPLD - CC703S for further information.

    2)

    SRST

    S6.2 /

    S2

    S6.4

    		IN

    Push button

    SRST
    JB3

    JB2.56

    		OUT
    Soft reset push button for SoM.

    Push button

    CM1S2.
    1CM1SC.BANK-1.75
    8IN
    S2.

    DIP Switch 2)

    CM0
    SC.BANK-1.76
    S2.7IN
    S2.3

    DIP Switch 2)

    JTAGEN
    SC.BANK-0.120
    S2.6IN
    S2.4

    DIP Switch 2)

    MIO0
    JB1
    S2.
    88
    5IN

    DIP Switch 2)

    VCCIOAJ5.2
    VCCIOAJB1.10 / JB1.12 / J1B.VCCIOA
    INSoM IO Bank supply 3)
    VCCIOB
    INOUT
    J8.2
    VCCIOBJB2.2 / JB2.4 / J1B.VCCIOB
    INSoM IO Bank supply 3)
    VCCIOC
    INOUT
    J9.2
    VCCIOCJB2.6 / J2B.VCCIOC
    INSoM IO Bank supply 3)
    VCCIOD
    INOUT
    J10.2
    VCCIODJB2.8 / JB2.10 / J2B.VCCIODINOUT
    INSoM IO Bank supply 3)
    J3.9
    SD_CD
    SC.Bank-1.93
    J3.9INSD Card socket
    Interrupt
    Detect Signal
    Software defined Signals

    Connector.Pin

    Signal Name

    Endpoint

    Direction1)DescriptionJB3.54VBUS_V_ENU1.4INEnable from SoMJB3.56USB-VBUSU1.8 → R5 (12K) →
    VBUS_V_ENJB3.54INEnables USB Host Bus Voltage
    USB-VBUSJB3.56OUTSignal to SoM
    U1.5USB_OCSC.BANK-1.73INSignal to SC
    RESINJB2.17
    RESINSC.BANK-0.119INOUTBetween SoM and SC
    OUTReset signal 2)
    EN1JB1.27
    EN1SC.BANK-1.81INOUT
    OUTPower enable signal 2)
    PGOOD
    Between SoM and SC
    JB1.29
    PGOODSC.BANK-1.82
    INOUT
    Between SoM and SC
    Power good and/or Boot mode select signal 2)
    MODEJB1.31
    MODESC.BANK-1.83INOUTBetween SoM and SCJB1.8NOSEQSC.BANK-1.78INOUTBetween SoM and SC
    INOUTBoot mode select signal 2)
    NOSEQJB1.8INOUT

    Power Management and/or Select JTAG target on the SoM 2)

    PROGMODEJB1.90INOUTSelect JTAG target on the SoM 2)
    MIO14 / MIO15
    JB1.90PROGMODESC.BANK-1.104INOUTBetween SoM and SC
    JB1.91 / JB1.86
    MIO14 / MIO15To SC.Bank-1.105 / SC.Bank-1.95
    INOUTUART to
    SoM JB1.100 / 98
    SoM (FT2230H) 2)
    MIO12 / MIO13
    To SC.Bank-1.
    JB1.100 /
    SC.Bank-1.99J1A.MIO10-SCL / J1A.MIO11-SDA
    JB1.98INOUT
    Second UART to SoM 
    UART to SoM (FT230XQ) 2)

    MIO10-SCL / MIO10

    MIO10-SDA / MIO11

    J1A.A1 / JB1.96

    / SC.Bank-1.MIO10

    J1A.A2 / JB1.94

    / SC.Bank-1.MIO11

    		INOUTI2C
    with 5.1 kOhm pull-up resistors.
    To SoM and SC
    bus 2)
    TMS_B / TDI_B / TDO_B / TCK_B

    JB2.94 / JB2.96 / JB2.98 / JB2.100

    		Signal-dependent

    JTAG configuration and debugging interface.

    JTAG reference voltage: VCCJTAG

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    2) Firmware dependent. Refer to TEB2000 CPLD Firmware for further information.
    3) Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information.

    Power and Power-On Sequence

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    Enter the default value for power supply and startup of the module here.

    • Order of power provided Voltages and Reset/Enable signals

    Link to Schematics, for power images or more details


    Power Rails

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    List of all power rails which are accessible by the customer

    • Main Power Rails and Variable Bank Power


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    From SoMFrom SoMFrom SoM
    Power Rail Name/ Schematic NameConnector + .PinDirection1)Notes
    5VIN J13.1IN
    5VIN J2A.5VIN A1 / J2A.A2OUT
    3.3VJ1C.3.3V C31 / J2C.3.3V C31 /
    JB1.2 /  JB1.4/  JB1.6/  JB1.14/  JB1.16 /
    JB2.1 / JB2.3 / JB2.5 / JB2.7    		OUT
    USB-VBUS_RJ6.1 / J12.1 / OUT
    USB-VBUSJB3.56OUT

    M1.8VOUT

    		JB1.40 / J11.1INFrom SoM

    M1.8VOUT

    		J5.3 / J8.3 / J9.3 / J10.3 / J11.1OUT

    M3.3VOUT

    		JB2.9 / JB2.11IN

    M3.3VOUT

    		J5.1 / J8.1 / J9.1 / J10.1 /
    J1C.M3.3VOUT C32 / J2C.M3.3VOUT;C32    		OUT

    VCCJTAG

    		JB2.92IN

    ETH-VCC

    		JB1.13IN

    ETH-VCC

    		J14A.1OUT
    VCCIOAJB1.10 / JB1.12INAMD SoM abhängigVCCIOAJ5.2 / J1B.VCCIOAB1OUTUse jumper J5  to select between M1.8VOUT or M3.3VOUT.

    Selection via J5 2)

    VCCIOB

    JB2.2 / JB2.4

    		INAMD SoM abhängigVCCIOBJ8.2

    / J1B.

    VCCIOB

    B32

    		OUTUse jumper J8  to select between M1.8VOUT or M3.3VOUT.

    Selection via J8 2) 

    VCCIOCJB2.6INAMD SoM abhängig / J2B.B32
    		OUT

    Selection via J9 2)

    		VCCIOCJ9.2 / J2.VCCIOCOUTUse jumper J9  to select between M1.8VOUT or M3.3VOUT.

    VCCIODJB2.8 / JB2.10INAMD SoM abhängig / J2B.B1OUT

    Selection via J10 2)

    		VCCIODJ10.2 /  J2.VCCIODOUTUse jumper J10  to select between M1.8VOUT or M3.3VOUT.

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.
    Recommended Power up

    2) Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information.

    Recommended Power up Sequencing

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    SequenceNet nameRecommended Voltage RangePull-up/down

    Description

    		Notes
    0---Configuration signal setup.See Configuration and System Control Signals.
    15VIN
    5V
    5 V (± 5 %)-Main Power supply
    via J13 Barrel Plug 2.1 mm3.3
    .

    Carrier and SoM power supply.
    Minimal 1 A, maximal 4A. 

    Power consumption depends mainly on design and cooling solution.

    2M3.3VOUT / M1.8VOUT
    (JB2, 9, 11)
    3.3 V (± 3 %) /
    1.8 V (± 3 %)
    Schematic
    		3---
    -

    SoM generated

    voltage, 
    which signals operational readyness of the SoM.

    output voltages.

    These voltages can be used

    • to supply bank voltages,
    • to supply periphery and/or
    • as power good signal to enable external power regulators.

    Important: Consider maximum power consumption.

    3---
    Apply voltages to Carrier powered external IO 
    when voltages under point 2 are present.


    Board to Board Connectors

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    • This section is optional and only for modules.

    • use "include page" macro and link to the general B2B connector page of the module series,

      For example: 6 x 6 SoM LSHM B2B Connectors

      Include Page
      PD:6 x 6 SoM LSHM B2B ConnectorsPD:
      6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:4 x 5 SoM LSHM B2B ConnectorsPD:
    4 x 5 SoM LSHM B2B Connectors

    Technical Specifications


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    List of all power rails which are accessible by the customer

    • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

    Absolute Maximum Ratings *)

    This Table shows the real values and reasons for the limits, so that they do not get lost.

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    Power Rail / Schematic NameDescriptionMinMaxUnitNotes
    5VIN
    Power Rail / Schematic NameDescriptionMinMaxUnitNotesReason for the limit
    SD Card Limits

    Limits for 3.3 V and 1.8 V SD Card supply. Only Recommanded values are given.

    Rec:
    2.7
    1.7

    Rec:
    3.6
    1.95

    		VSupplied by M3.3VOUT and optional by M1.8VOUT, when SD IO Jumper is to 1.8 V.







    5VIN

    Carrier supply voltage rail before the input

    voltage protection activates.0
    12

    protection. 

    Abs:
    -40
    Rec:
    4.75

    		Abs:
    60
    Rec:
    5.5    		VVoltages
    in
    outside of the range 4.06 to 5.58 V will trigger the input protection.
    Rec.= USB Bus Voltage
    VCCIOA
    Intended as Supply Voltage for a

    SoM IO Bank

    . Connects the external VG96 IO to the SoM.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    --VVoltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

    Voltage.

    		--VVoltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO.
    VCCIOBSoM IO Bank Voltage.
    VCCIOB

    Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.
    --VVoltage
    intended to
    can be supplied by
    either
    M1.8VOUT
    or
    , M3.3VOUT or externally by VG96 IO.
    VCCIOC
    Supplies SC Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    SoM and Carrier Sc IO Bank

    2. Connects the external VG96 IO to the SoM and the Carrier SC.

    2  voltage.

    Abs:


    -0.5

    Rec:
    1.14

    Abs:
    3.75

    V

    Limited by Absolute Maximum Values of the Sc.

    VCCIOD

    Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

    Rec:
    3.6

    		V

    Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO.

    System Controller Limits:
    Abs:         -0.5 to 3.75
    Rec VCC:  2.375 to 3.6
    Rec IO:    1.14 to 3.6

    Limited by Absolute Maximum Values of the Sc.

    VCCIODSoM IO Bank Supply Voltage
    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96
    .--VVoltage
    intended to
    can be supplied by
    either
    M1.8VOUT
    or
    , M3.3VOUT or externally by VG96 IO.
    M1.8VOUT

    SoM supplied voltage.

    Range based on Carrier (± 3 %). Consult SoM requirements.


    		Abs:
    -0.3
    M3.3VOUT +0.3 VV

    Voltage limited by Q1/MP5077GG-Z Enabled Pin.

     –0.3V to Vcc +0.3 V
    (M3.3VOUT-max = 4.6)

    Abs:
    4.9    		V

    When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75

    Connected SD cards might be destroyed above 1.95

    V.


    M3.3VOUT

    SoM supplied voltage.

    Range based on Carrier (± 3 %). Consult SoM requirements.
    Abs:
    -0.5    		Abs:
    4.6    		V

    Limited by U2/TXS02612RTWR.

    Connected SD cards might be destroyed above 3.6 V.

    VCCJTAG

    Supplies SC IO Bank 3.

    JTAG Reference Voltage from SoM. Consult SoM documentation.

    -0.53.75VETH-VCCETH Bias Voltage from SoM.
    Consult SoM documentation.--V

    *) Stresses beyond those listed under TEB2000 TRM - New Carrier-Board may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
       or any other conditions beyond those indicated under TEB2000 TRM - New Carrier-Board. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

    Recommended Operating Conditions

    Temperature Range:

    This carrier board is capable to be operated at industrial grade temperatures.

    • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

    Please check the operating temperature range of the mounted SoM and peripheral devices, which determines the operating temperature range of the overall system.

    The Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    Voltage Rails:

    When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75 V.

    When suppling a SD Card,
    SD Card limits are 2.7 to 3.6 V.

    M3.3VOUT is limited by U2 in the range -0.5 to 4.6 V.

    VBATDependent on SoM requirements.--V

    VCCJTAGSoM supplied JTAG Reference Voltage for Carrier SC IO Bank 3.

    Abs:
    -0.5

    		Abs:
    3.75    		V

    System Controller Limits:
    Abs:         -0.5 to 3.75
    Rec VCC:  2.375 to 3.6
    Rec IO:    1.14 to 3.6

    		Limited by Absolute Maximum Values of the Sc.
    ETH-VCCETH Bias Voltage from SoM.--V

    Absolute Maximum Ratings *)

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    Power Rail / Schematic NameDescriptionMinMaxUnit
    		Notes
    5VIN

    Carrier supply voltage rail before the input voltage protection activates.

    4.755.25VTolerance is ±5 %.VCCIOA

    Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    1.75

    3.4

    V

    Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

    VCCIOB

    Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    1.753.4V

    Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

    VCCIOC

    Supplies SC IO Bank 2. Connects the external VG96 IO to the SoM and the Carrier SC.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    1.2

    3.4

    V

    Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

    VCCIOD

    Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

    Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

    1.753.4V

    Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

    M1.8VOUT

    SoM supplied voltage.
    Range based on Carrier (± 3 %). Consult SoM requirements.

    1.751.85V

    Tolerance is ±3 %.

    M3.3VOUT

    SoM supplied voltage.

    Range based on Carrier. Consult SoM requirements.

    3.23.4VTolerance is ±3 %.

    Main input power supply

    		-0.360V
    VCCIOA 1) 2)

    Module power supply.

    		--V
    VCCIOB 1) 2)Module power supply.--V
    VCCIOC 1) 2)

    Module and Carrier power supply.

    		-0.53.75V
    VCCIOD 1) 2)Module power supply.--V
    M1.8VOUT

    Module and carrier power supply.

    		-0.31.95V
    M3.3VOUT

    Module and carrier power supply.

    -0.3

    3.6

    		V
    VCCJTAG

    JTAG Reference Voltage

    		-0.53.75V
    ETH-VCCPower supply for ETH connection.--V