Page History

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Products Affected

This change affects all Trenz Electronic TE0729 SoMs: TE0729-02*.

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Impact: Power supply starts only if voltage rail VIN is in adequate voltage range.

#5

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Type: Schematic Change

Reason: EOL of Component.

Impact: None.

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Changed power net name from 1.5V to DDR_VDD.

Type: Schematic Change

Reason: Improve name handlingnaming.

Impact: None.

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#6 Changed power sequencing.

Type: Schematic Change

Reason: Follow AMD and Texas Instruments recommendation.

Impact: Voltage rails start in other orderCheck that the new power-up sequence fits your requirements. Voltage supervisor (U4) enables 1V voltage rail (DCDC U23) via signal EN_Module. 1V DCDC (U23) enables 1.8V voltage rail (DCDC U25) via signal PG_1V0. 1.8V DCDC (U25) enables 2.5V (DCDC U24) and DDR_VDD (DCDC U26) voltage rails via signal PG_1V8. Voltage rail 3.3V (load switch Q1) is logical AND-enabled via power good signal PG_2V5_3V3 from voltage rail 2.5V DCDC (U24) and DDR_VDD DCDC (U26) via diode (D4) and CPLD (U6) signal EN_3V3 via diode (D5).

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#7 Added bidirectional level shifter (U7) and capacitors (C185, C186) to separate power domains for signal FPGA_IO. Added fallback resistor (R91).

Type: Schematic Change

Reason: Improve power domain handling for signal FPGA_IO.

Impact: None.

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#8 Added diode (D3) between U21 pin 3 net nRST_in and voltage rail 3.3V.

Type: Schematic Change

Reason: Protect manual reset pin.

Impact: None.

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#9 Added option to improve noise immunity for signal nRST_in via capacitor C187 (default: not assembled).

Type: Schematic Change

Reason: Improve noise immunity in needed cases.

Impact: None.

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#10 Connected exposed pad for SDIO port expander (U15) to GND.

Type: Schematic Change

Reason: Improve thermal situation.

Impact: None.

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#11 Added additional decoupling capacitors C166...C179.

Type: Schematic Change

Reason: Improve decoupling.

Impact: None.

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#12 Changed 10 µF capacitors (C36, C86) to 22 µF.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

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#13 Changed 22 µF capacitors (C117, C121,

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C125, and C127) from size 0806 to 0603.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

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#14 Changed capacitor (C144) from 470 nF, 6.3 V, X5R, 20 % to 100 nF, 16 V, X7R, 10 %.

Type: Schematic Change

Reason: Increase battery input voltage range.

Impact: None. Changes in electrical characteristics.

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#15 Pulled-up board revision signal (FPGA U2 pin H17) and updated board revision documentation.

Type: Schematic Change

Reason: Update revision information.

Impact: None. Firmware reflects it but custom firmware needs to be updated by customer.

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#16 Changed fiducials to standard fiducial type.

Type: Schematic Change

Reason: Use standard fiducials.

Impact: None.

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#17 Removed track-it traceability pad S/N.

Type: Schematic Change

Reason: EOL of Component.

Impact: None.

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#18 Added testpoints TP1...TP41.

Type: PCB Change

Reason: Improve signal monitoringtesting.

Impact: None.

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#19 Added serial number box print on bottom overlay.

Type: PCB Change

Reason: Required for manufacturing.

Impact: None.

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#20 Signal trace lengths changed

Type: PCB change

Reason: Result of changes above.

Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE0729 series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#21 Added revision history, block and power diagram. Updated page count and order. 

Type: Documentation Update

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Production Shipment Schedule

From July 20252024, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

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