Page History

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• Intel Cyclone 10LP 10CL025 FPGA SoC

• 8 MByte SDRAM

• 2 MByte serial configuration memory

• ST Microelectronics LIS3DH 3-axis accelerometer
  
• JTAG and UART over Micro USB2 connector
• 1x6 pin header for JTAG access to FPGA SoC
• 1x PMOD header providing 8 GPIOs

• 2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs

• 1x 3-pin header providing 2 GPIOs

• 8x user LEDs

• 1x user push button
• 35.3V 0V single power supply with on-board voltage regulators
• Size: 61.5 x 25 mm
  
  

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1. Intel Cyclone 10LP 10CL025 FPGA SoC, U1
2. Winbond W9864G6JT 8 Mbyte SDRAM 166MHz, U2
3. Intel EPCQ16ASI8N 2 MByte serial configuration memory, U5
4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
5. FTDI USB2 to JTAG/UART adapter, U3
6. Configuration EEPROM for FTDI chip, U9
7. 12.0000 MHz oscillator, U7
8. 8x red user LEDs, D2 ... D9
9. Red LED (Conf. DONE), D10
10. Green LED (indicating supply voltage), D1
11. Push button (user), S2
12. Push button (reset), S1
13. Micro USB2 B socket (receptacle), J9
14. 1x14 pin header (2.54mm pitch), J2
15. 1x6 pin header (2.54mm pitch), J4
16. 2x6 Pmod connector, J6
17. 3-pin header (2.54mm pitch), J3
18. 1x14 pin header (2.54mm pitch), J1

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By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.

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Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table 3: General overview of FPGA Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

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On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N (EPCQ16SI8N in board revision TEI0003-02A) with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.

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On the TEI0003 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

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Power Consumption

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There is no specific or special power-on sequence, just one single power source is needed.

Power Rails

Table 13: Connector power pin description

Bank Voltages

Table 14: FPGA SoC VCCO bank voltages

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Table 1315: Absolute maximum ratings

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Table 1416: Recommended operating conditions

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• Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.65mm

• Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

      Figure 4

Revision History

Hardware Revision History

Table 1217: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Table 1318: Document change history

Disclaimer

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