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The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel a Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operationuser application, 8 MByte SDRAM and a 3-axis accelerometer.

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Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.

Key Features

• Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• ST Microelectronics LIS3DH 3-axis accelerometer
  
• JTAG and UART over Micro USB2 connector
• 1x6 pin header for JTAG access to FPGA SoC
• 1x PMOD header providing 8 GPIOs

• 2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs with 7 analog inputs as alternative function

• 1x 3-pin header providing 2 analog inputs or 1 GPIO

• 8x user LEDs

• 1x user push button
• 5.0V single power supply with on-board voltage regulators
• Size: 61.5 x 25 mm
  
  

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Main Components

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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

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Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG pin header

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Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

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Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

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Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

Table 11: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

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Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

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Table 13: Connector power pin description

Bank Voltages

Table 14: FPGA SoC VCCO bank voltages

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Table 15: Absolute maximum ratings

Recommended Operating Conditions

Table 16: Recommended operating conditions

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Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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v.17

Table 18: Document change history

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