The module has a 24 MHz SMD clock oscillator providing a clock source for both the EZ-USB FX2LP USB FX2 microcontroller (XTALIN) and the FPGA as detailed in the table below.
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The DCMs of the FPGA can be used to synthesize arbitrary clock frequencies from any on-board clock network, differential clock input pair or single-ended clock input. For further reference, please read Xilinx DS485:Digital Clock Manager (DCM) Module and the DCM chapter in Xilinx UG331: Spartan-3 Generation FPGA User Guide.
The IFCLK line synchronizes the communication between the EZ-USB FX2LP USB FX2 microcontroller and the FPGA as detailed in the table below.
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The module has a main SMD clock oscillator providing a clock source for the FPGA as detailed in the table below.
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Standard frequency is 100 MHz. Should you wish or need another main clock oscillator frequency, please contact Trenz Electronic. The lower the main clock frequency, the lower the module power consumption. Moreover, as the main clock is preferably used as DDR SDRAM clock, a lower clock frequency makes easier for the development tools to meet the timing requirements (particularly for DDR SDRAM).
TE0320 has a watchdog timer that is periodically triggered by a positive or negative transition of the watchdog input (WDI) signal. When the supervising system fails to retrigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the watchdog output becomes active and asserts the master reset (/MR) signal. This event also reinitializes the watchdog timer.
If resistors R135 and R165 R136 are not populated, the watchdog is disabled.
If resistors R135 and R165 R136 are populated, the watchdog can be enabled . In this case there are still two options.(or not).
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Any other combination of resistors R135 and R136 is not supported. |
If resistors R135 and R136 are populated, there is two configuration possible.
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Figure 41: R135 (bottom side). | Figure 42: R136 (top side). |
Warning |
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Any other combination of resistors R135 and R136 is not supported. |