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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

Date	Version	Changes	Author
2023-02-07	2.2	added column 'Firmware release' in 'Document Change History' table changed template revision from list to table	ma
-	2.1	Fix problem with pdf export and side scroll bar	-
-	2.0	add fix table of content add table size as macro removed page initial creator	-

Overview

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CPLD Device with designator U46: 10M08SAU169

Warning
For use with the TEBT0865-01 carrier board a small hardware patch on TEBT0865-01 is required. PCN-20240909 TE0865-02 CPLD Firmware Update / TEBT0865-01 Hardware Patch

Feature Summary

something to have access to CPLD to read out status of Power managementJTAG_UART
Power management
Reset
I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

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Port Description

Name / opt. VHD Name	Direction	Pin	I/O Bank	Pullup/Down

Bank Power

Description

I/O Standard	Current Strength	Description
JTAGEN	in	E5		--	3.3V		fixed to 3.3V
TCK_MAX10	in	G2		--

3.3V

2.5V (default)	12mA (default)	JTAG
TMS_MAX10	in	G1		--

3.3V

2.5V (default)	12mA (default)	JTAG
TDO_MAX10	out	F6		--

3.3V

2.5V (default)	12mA (default)	JTAG
TDI_MAX10	in	F5		--

3.3V

2.5V (default)	12mA (default)	JTAG

JTAG

EN

PG_

VTT

1V2_PL_DDR

in

H5

out

2	weak pull-up

J2

3.3V LVCMOS

Enable signal for TPS51206 (U26)
VTT: VTT_DDR_PL
VTTREF: VREFA_DDR_PL

2mA (default)

PowerGood output signal from TPS82130 (U24)
- open drain output, pull-up resistor needed
- PG: PG_+1.2V_PL_DDR
- EN: EN_+1.2V_PL_DDR
- VOUT: +1.2V

EN_2V5_PL_DDRoutJ13.3V LVCMOS

Enable signal for TPS82130 (U22)

VOUT: +2.5V

- _PL_DDR

PG

: PG_+2.5V_PL_DREN_1V2_PL_DDRout

_VCCINT

in

N3

2

weak pull-up

H4

3.3V LVCMOS

Enable signal for TPS82130 (U24)
VOUT: +1.2V_PL_DDR
PG: PG_+1.2V_PL_DR

PG_1V2_PL_DDRinH5

2mA (default)	PowerGood output signal from LTM4700 (U20) open drain output, pull-up resistor needed PGOOD0/1: PG_VCCINT RUN0/1: EN_VCCINT
LTM_FAULT	in	N2	2

weak pull-up

3.3V LVCMOS

PowerGood output

2mA (default)

FAULT signal from

TPS82130

LTM4700 (

U24)EN_1V8_PS_AUXout

U20) open drain input and output, pull-up resistor needed FAULT0/1: LTM_FAULT
M_SDA	inout	M3	2	--

M2

3.3V LVCMOS

Enable signal for TPS72018 (U43)
VOUT: +1.8V_AUX_PS

PG_SOMout

2mA (default)	connected to level shifter TXS0102 (U12) connected to EEPROM 24AA025 (U14) connected to SLS32AIA (U16) connected to ATECC608B-MAH (U19) connected to LTM4700 (U20)
EN_SOM	in	K1	2

M1

weak pull-up

3.3V LVCMOS

PowerGood output signal connected to J2B (D51)

2mA (default)

EN_SOM input_signal
in TEBT0865:

enable signal for TPS82130 (U2) → Carrier_+1.8V

PWRGD signal for TPS54240 (U14) → Carrier_+1.8V

SC_EXT4 signal connected to J2B (D54)
SC_EXT_3	in	L2	2	--

PG_VCCINTinN3weak pull-up

3.3V LVCMOS

PowerGood output signal from LTM4700 (U20

2mA (default)

LTM_FAULT

SC_EXT3 input signal connected to J2B (D53)
in

N23.3V LVCMOS

FAULT signal from LTM4700 (U20)

SC_EXT_2out

TEBT0865: Overcurrent Signal from TPS2051 (U9) not used in CPLD
EN_VTT_PL_DDR	out	J2	2	--

L3

3.3V

LVCMOS

SC_EXT2 output signal connected to J2B (D52)
in TEBT0865:
- enable signal for USB TPS82130 (U12)
Deactivated on delivery

M_SDAinoutM33.3V LVCMOS

connected to level shifter TXS0102 (U12)
connected to EEPROM 24AA025 (U14)
connected to SLS32AIA (U16)
connected to ATECC608B-MAH (U19)

MRoutK23.3V LVCMOS

Manual Reset
actual configured as output and set to 1.
Should be an input for monitoring???

LVTTL	8mA (default)	Enable signal for TPS51206 (U26) S3/S5: EN_VTT_DDR_PL VTT: VTT_DDR_PL VTTREF: VREFA_DDR_PL
EN_2V5_PL_DDR	out	J1	2	--	3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U22) EN: EN_+2.5V_PL_DR VOUT: +2.5V_PL_DDR PG: PG_+2.5V_PL_DR
EN_1V2_PL_DDR	out	H4	2	--	3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U24) EN: EN_+1.2V_PL_DR VOUT: +1.2V_PL_DDR PG: PG_+1.2V_PL_DR
EN_1V8_PS_AUX	out	M2	2	--	3.3V LVTTL	8mA (default)	Enable signal for TPS72018 (U43) EN: EN_+1.8V_AUX_PS VOUT: +1.8V_AUX_PS
PG_SOM	out	M1	2	--	3.3V LVTTL	8mA (default)	PG_SOM output signal connected to J2B (D51) in TEBT0865: enable signal for TPS82130 (U2

EN_SOMinK1weak pull-up3.3V LVCMOS

SC_EXT4 input signal connected to J2B (D54)

in TEBT0865:PG signal from TPS82130 (U3

- ) → Carrier_+1.8V

PWRGD

- enable signal for TPS54240 (

U15

- U14) → Carrier_+1.8V

SC_EXT_

3in

2

out

L3

2

--

L2

3.3V LVCMOS

2mA (default)

SC_

EXT3 input

EXT2 output signal connected to J2B (

D53

D52)
in TEBT0865:

Overcurrent Signal from TPS2051 (U9)

enable signal for USB TPS82130 (U12) Deactivated on delivery Can be activated via I2C (see reference design)
MR	inout	K2	2

SMB_ALERTnin L43.3V LVCMOS

Alert signal from LTM4700 (U20)

PG_2V5_PL_DDRin L5

weak pull-up

3.3V LVCMOS

PowerGood output signal from TPS82130 (U22)

EN_LTM_RUNPout

2mA (default)	Manual Reset will be released after power group 6 is enabled

SMB_ALERTn	in	L4	3	--

M5

3.3V LVCMOS

RUNP

2mA (default)

nAlert signal from LTM4700 (U20)

enables board bias circuit to supply IC and to drive the MOSFET when the SVin is higher than 7V.

Needs to be '1' ; Tie to ground to disable the bias circuit when Vin is less than 5,75V

not used in CPLD
PG_2V5_PL_DDR	in	L5	3	weak pull-up

M_SCL inoutM4

3.3V LVCMOS

connected to level shifter TXS0102 (U12)
connected to EEPROM 24AA025 (U14)
connected to SLS32AIA (U16)
connected to ATECC608B-MAH (U19)

nRST_SYS outK53.3V LVCMOS

System reset output signal, resets eMMC, ETH-Phy and USB-Phy

2mA (default)	PowerGood output signal from TPS82130 (U22) open drain output, pull-up resistor needed PG: PG_+2.5V_PL_DR EN: EN_+2.5V_PL_DDR VOUT: +2.5V_PL_DDR
M_SCL	inout	M4	3	--	3.3V LVCMOS	2mA (default)	connected to level shifter TXS0102 (U12) connected to EEPROM 24AA025 (U14) connected to SLS32AIA (U16) connected to ATECC608B-MAH (U19) connected to LTM4700 (U20)
nRST_SYS	out	K5	3		3.3V LVCMOS	2mA (default)	RST_SYSn System reset output signal, resets eMMC, ETH-Phy and USB-Phy will be released after power group 6 is enabled

EN_0V9_GTH_AVCCout
N53.3V LVCMOS

Enable signal for TPS82130 (U35)

EN_0V9_GTY_AVCCout
N43.3V LVCMOSEnable signal for TPS82130 (U38)


PG_1V2_PS_DDR	in	M7	3	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U25) open drain output, pull-up resistor needed PG

_0V9_GTH_AVCC

- : PG_+1.2V_PS_DDR
- EN: EN_+1.2V_PS_DDR
- VOUT: +1.2V_PS_DDR

inN6weak pull-up3.3V LVCMOSPowerGood output signal from LT8642 (U35)

PG_0V9_

GTY

GTH_AVCC

in

N8

N6

3

weak pull-up

3.3V LVCMOS

2mA (default)

PowerGood output signal from LT8642 (

U38

U35)

EN_3V3_SWout
N73.3V LVCMOS

enable signal for SIP32408 (U52)

EN_1V2_PS_PLLout
J63.3V LVCMOS

Enable signal for TPS72012 (U42)

PG_1V8_PS_GTR_AVTT

in

PG: PG_+0.9V_GTH_AVCC EN/UV: EN_+0.9V_GTH_AVCC SW: +0.9V_GTH_AVCC open drain output
PG_0V9_GTY_AVCC	in	N8	3

M9

weak pull-up

3.3V LVCMOS

2mA (default)

PowerGood output signal from

TPS82130

LT8642 (

U47

U38) PG: PG_+0.9V_GTY_AVCC EN/UV: EN_+0.9V_GTY_AVCC SW: +0.9V_GTY_AVCC open drain output
PG_1V8_PS_GTR_AVTT	in

M8

M9

3

weak pull-up

3.3V LVCMOS

2mA (default)

PowerGood output signal from TPS82130 (

U41)EN_2V5_PS_DDRout
M133.3V LVCMOS

Enable signal for TPS82130 (U23)

PG_1V2_GTY_AVTT in

U47) open drain output, pull-up resistor needed PG: PG_+1.8V_GTR_AVTT_PS EN: EN_+1.8V_GTR_AVTT_PS VOUT: +1.8V_GTR_AVTT_PS
PG_1V8	in	M8	3

N9

weak pull-up

3.3V LVCMOS

2mA (default)

PowerGood output signal from

LT8642

TPS82130 (

U39)EN

U41)
- open drain output, pull-up resistor needed
- PG: PG_+1.8V
- EN: EN_+1.8V
- VOUT: +1.8V

PG_1V2_GTY_AVTT

out

in

N9

3

weak pull-up

N10

3.3V LVCMOS

Enable signal for

2mA (default)

PowerGood output signal from LT8642 (U39)

M_INT L113.3V LVCMOS

PG: PG_+1.2V_GTY_AVTT EN/UV: EN_+1.2V_GTY_AVTT SW: +1.2V_GTY_AVTT open drain output
M_INT	in	L11	3	--

EN_1V8_VCC_ADCout
M11

3.3V LVCMOS

Enable signal for TPS72018 (U49)

VOUT: +1.8V_VCCADC

2mA (default)	not used in CPLD
PG_0V85_PS_GTR_AVCC	in	K8	3	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS74801 (U48)

EN_VTT_PS_DDRout
J83.3V LVCMOS

Enable signal for TPS51206 (U27)
VTT: VTT_DDR_PS
VTTREF: VREFA_DDR_PS

EN_1V8out
L103.3V LVCMOS

Enable signal for TPS82130 (U41)

EN_1V8_GTY_AUXout
M103.3V LVCMOS

Enable signal for TPS72018 (U40)

VOUT: +1.8V_GTY_AUX

open drain output, pull-up resistor needed PG: PG_+0.85V_PS_GTR_AVCC EN: EN_+0.85V_PS_GTR_AVCC OUT: +0.85V_PS_GTR_AVCC
PG_2V3	in	N12	3	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U45)

EN_1V8_GTR_AVTT_PS

out
K103.3V LVCMOS

enable signal for TPS82130 (U47)

EN_1V8_GTH_AUX

out
K113.3V LVCMOS

enable signal for TPS72018 (U37)
VOUT: +1.8V_GTH_AUX

EN_1V8_AUX

out
K123.3V LVCMOS

enable signal for TPS82130 (U50)

EN_1V2_GTH_AVTT

out
J123.3V LVCMOS

enable signal for LT8642 (U36)

PG_3V3_SW

inJ9weak pull-up3.3V LVCMOS

output voltage from secondary power SIP32408 (U52)

EN_1V2_PS_DDR

out
J133.3V LVCMOS

enable signal for TPS82130 (U25)

EN_0V85_GTR_AVCC_PS

out
H133.3V LVCMOS

enable signal for TPS74801 (U48)

PG_1V2_GTH_AVTT

inH9weak pull-up3.3V LVCMOS

PowerGood output signal from LT8642 (U36)

EN_VCCINT

out
H83.3V LVCMOS

enable signal for LTM4700 (U20)

EN_2V3

out
G133.3V LVCMOS

enable signal for TPS82130 (U45)

PG_1V8_AUX

inG12weak pull-up3.3V LVCMOS

PowerGood output signal from TPS82130 (U50)

PG_2V5_PS_DDR

inL13weak pull-up3.3V LVCMOS

PowerGood output signal from TPS82130 (U23)

Functional Description

Power

All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.

The power-up sequence corresponds to AMD's recommendations and is shown in the table below:

Power Group

Power enable signal

(CPLD output signal)

Power good signal

(CPLD input signal)

Notes0

EN_VCCINT

PG_VCCINT

--

EN_2V3

PG_2V3

--

EN_3V3_SW

PG_3V3_SW

+3.3V_SW output signal from U52

1

EN_1V8

PG_1V8

--

EN_1V8_AUX

PG_1V8_AUX

--

EN_1V8_PS_AUX

--

EN_1V2_PS_PLL

--

EN_0V9_GTH_AVCC

PG_0V9_GTH_AVCC

--

EN_0V9_GTY_AVCC

PG_0V9_GTY_AVCC

--

EN_1V8_VCC_ADC

--

2
EN_1V2_PS_DDRPG_1V2_PS_DDR--
EN_1V2_PL_DDRPG_1V2_PL_DDR--
EN_1V2_GTH_AVTTPG_1V2_GTH_AVTT--
EN_1V2_GTY_AVTTPG_1V2_GTY_AVTT--

3

EN_VTT_PS_DDR

--

EN_0V85_PS_GTR_AVCC

PG_0V85_PS_GTR_AVCC

--

EN_VTT_PL_DDR

--

EN_2V5_PL_DDR

PG_2V5_PL_DDR

--

EN_2V5_PS_DDR

PG_2V5_PS_DDR

--

EN_1V8_GTH_AUX

--

EN_1V8_GTY_AUX

--

4

EN_1V8_PS_GTR_AVTT

PG_1V8_PS_GTR_AVTT

--

Power Group

Power enable signal

(CPLD output signal)

Power good signal

(CPLD input signal)

Notes

0

--

EN_SOM

1

EN_VCCINT

PG_VCCINT

--

EN_2V3

PG_2V3

--

EN_3V3_SW

PG_3V3_SW

+3.3V_SW output signal from U52

2

EN_1V8

PG_1V8

--

EN_1V8_AUX

PG_1V8_AUX

--

EN_1V8_PS_AUX

--

EN_1V2_PS_PLL

--

EN_0V9_GTH_AVCC

PG_0V9_GTH_AVCC

--

EN_0V9_GTY_AVCC

PG_0V9_GTY_AVCC

--

EN_1V8_VCC_ADC

--

3
EN_1V2_PS_DDRPG_1V2_PS_DDR--
EN_1V2_PL_DDRPG_1V2_PL_DDR--
EN_1V2_GTH_AVTTPG_1V2_GTH_AVTT--
EN_1V2_GTY_AVTTPG_1V2_GTY_AVTT--

4

EN_VTT_PS_DDR

--

EN_0V85_PS_GTR_AVCC

PG_0V85_PS_GTR_AVCC

--

EN_VTT_PL_DDR

--

EN_2V5_PL_DDR

PG_2V5_PL_DDR

--

EN_2V5_PS_DDR

PG_2V5_PS_DDR

--

EN_1V8_GTH_AUX

--

EN_1V8_GTY_AUX

--

5

EN_1V8_PS_GTR_AVTT

PG_1V8_PS_GTR_AVTT

--

6

PG_SOM

--

JTAG UART

As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.

The command "nios2-terminal.exe" in the NIOS II command shell is used to output the power good signals and the revision of the CPLD firmware and the PCB.

I2C interface

CPLD firmware consists of an I2C Slave to Avalon-MM Master Bridge Intel FPGA IP i2c t GPIO block. This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20. In this case related i2c bus is bus 1.

RegisterDirection in CPLDAddressGPIO_input[7:0]Output (reading from CPLD)0x00GPIO_input[15:8]Output (reading from CPLD)0x01GPIO_input[23:16]Output (reading from CPLD)0x02GPIO_input[31:24]Output (reading from CPLD)0x03GPIO_output[7:0]Input (writing to CPLD)0x00GPIO_output[15:8]Input (writing to CPLD)0x01GPIO_output[23:16]Input (writing to CPLD)0x02GPIO_output[31:24]Input (writing to CPLD)0x03

NOSEQ pin

This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:

NOSEQ pin as outputConditionCommand in linux console'1'GPIO_output(16) = '1'

i2cset -y 1 0x20 0x02 0x01

'0'GPIO_output(16) = '0'

i2cset -y 1 0x20 0x02 0x00

NOSEQ pin as inputDescriptionCommand in linux consoleReading state of NOSEQ pinGPIO_input(16) = NOSEQ

i2cget -y 1 0x20 0x02

Access to CPLD Registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

Register AddressDirection in CPLDRelated instruction in linux console to access the register0x00Output (reading from CPLD)i2cget -y 1 0x20 0x000x01Output (reading from CPLD)i2cget -y 1 0x20 0x010x0CInput (writing to CPLD)i2cset -y 1 0x20 0x00 <data>GPIO_output[15:8]Input (writing to CPLD)i2cset -y 1 0x20 0x01 <data>GPIO_output[23:16]Input (writing to CPLD)i2cset -y 1 0x20 0x02 <data>GPIO_output[31:24]Input (writing to CPLD)

i2cset -y 1 0x20 0x03 <data>

Some of these registers are using to show some information same as CPLD revision and boot mode while booting.

RegisterAddressrelated dataRead/write by userDescriptionGPIO_input[7:0]0x00CPLD REVISION (8 bits)NoGPIO_input[15:8]0x01"00" & BOOTMODE_GEN (2 bits) & PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits)No

BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC).

PUDC is the state of PUDC pin of FPGA.

CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high)

BOOT_MODE shows selected boot mode.

GPIO_input8[16]0x02NOSEQ pinYesRegisterAddressrelated dataDescriptionGPIO_output[16]0x02NOSEQ pinYes

If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:

InformationDisplayed in Linux consoleDescriptionCPLD RevisionCPLD_REV = <cpld revision>Boot mode selection procedureCPLD_BM = < bm selection procedure>

If boot mode via hardware is selected → Deactive(0)
If boot mode via software (in linux console or via FSBL code) is selected → Active(1)

Jed file that on CPLD is programmedBOOTMODE_GEN = < jed file type>

Jed file type can be one of the following types :
- (0) QSPI/SD
- (1) QSPI/JTAG
- (2) JTAG/SD
- (3) default QSPI/JTAG/SD/eMMC

PUDC pin statePUDC_MODE = <pudc state>

PUDC can have one of the following state:
- Pull-up activated (0)
- Pull-up deactivated (1)

open drain output, pull-up resistor needed PG: PG_+2.3V EN: EN_+2.3V VOUT: +2.3V
EN_LTM_RUNP	out	M5	3	--	3.3V LVTTL	8mA (default)	RUNP signal from LTM4700 (U20) enables board bias circuit to supply IC and to drive the MOSFET when the SVin is higher than 7V. Needs to be '1' ; Tie to ground to disable the bias circuit when Vin is less than 5,75V
EN_0V9_GTH_AVCC	out	N5	3	--	3.3V LVTTL	8mA (default)	Enable signal for LT8642 (U35) EN/UV: EN_+0.9V_GTH_AVCC PG: PG_+0.9V_GTH_AVCC SW: +0.9V_GTH_AVCC
EN_0V9_GTY_AVCC	out	N4	3	--	3.3V LVTTL	8mA (default)	Enable signal for LT8642 (U38) EN/UV: EN_+0.9V_GTY_AVCC PG: PG_+0.9V_GTY_AVCC SW: +0.9V_GTY_AVCC
EN_3V3_SW	out	N7	3	--	3.3V LVTTL	8mA (default)	enable signal for SIP32408 (U52) EN: EN_+3.3V_SW
EN_1V2_PS_PLL	out	J6	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS72012 (U42) EN: EN_+1.2V_PLL_PS OUT: +1.2V_PLL_PS
EN_2V5_PS_DDR	out	M13	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U23) EN: EN_+2.5V_PS_DDR PG: PG_+2.5V_PS_DDR VOUT: +2.5V_PS_DDR
EN_1V2_GTY_AVTT	out	N10	3	--	3.3V LVTTL	8mA (default)	Enable signal for LT8642 (U39) EN/UV: EN_+1.2V_GTY_AVTT PG: PG_+1.2V_GTY_AVTT SW: +1.2V_GTY_AVTT
EN_1V8_VCC_ADC	out	M11	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS72018 (U49) EN: EN_+1.8V_VCCADC VOUT: +1.8V_VCCADC
EN_VTT_PS_DDR	out	J8	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS51206 (U27) S3/S5: EN_VTT_DDR_PS VTT: VTT_DDR_PS VTTREF: VREFA_DDR_PS
EN_1V8	out	L10	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS82130 (U41) EN: EN_+1.8V PG: PG_+1.8V VOUT: +1.8V
EN_1V8_GTY_AUX	out	M10	3	--	3.3V LVTTL	8mA (default)	Enable signal for TPS72018 (U40) EN: EN_+1.8V_GTY_AUX OUT: +1.8V_GTY_AUX

PG_3V3_SW	in	J9	5	--	3.3V LVCMOS	2mA (default)	output voltage from secondary power SIP32408 (U52) OUT: +3.3V_SW EN: EN_+3.3V_SW
PG_1V2_GTH_AVTT	in	H9	5	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from LT8642 (U36) PG: PG_+1.2V_GTH_AVTT EN/UV: EN_+1.2V_GTH_AVTT SW: +1.2V_GTH_AVTT open drain output
PG_1V8_AUX	in	G12	5	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U50) open drain output PG: PG_+1.8V_AUX EN: EN_+1.8V_AUX VOUT: +1.8V_AUX
PG_2V5_PS_DDR	in	L13	5	weak pull-up	3.3V LVCMOS	2mA (default)	PowerGood output signal from TPS82130 (U23) open drain output PG: PG_+2.5V_PS_DDR EN: EN_+2.5V_PS_DDR VOUT: +2.5V_PS_DDR
EN_1V8_PS_GTR_AVTT	out	K10	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS82130 (U47) EN: EN_+1.8V_GTR_AVTT_PS PG: PG_+1.8V_GTR_AVTT_PS VOUT: +1.8V_GTR_AVTT_PS
EN_1V8_GTH_AUX	out	K11	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS72018 (U37) EN: EN_+1.8V_GTH_AUX OUT: +1.8V_GTH_AUX
EN_1V8_AUX	out	K12	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS82130 (U50) EN: EN_+1.8V_AUX PG: PG_+1.8V_AUX VOUT: +1.8V_AUX
EN_1V2_GTH_AVTT	out	J12	5	--	3.3V LVTTL	8mA (default)	enable signal for LT8642 (U36) EN/UV: EN_+1.2V_GTH_AVTT PG: PG_+1.2V_GTH_AVTT SW: +1.2V_GTH_AVTT
EN_1V2_PS_DDR	out	J13	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS82130 (U25) EN: EN_+1.2V_PS_DDR PG: PG_+1.2V_PS_DDR VOUT: +1.2V_PS_DDR
EN_0V85_PS_GTR_AVCC	out	H13	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS74801 (U48) EN: EN_+0.85V_PS_GTR_AVCC PG: PG_+0.85V_PS_GTR_AVCC OUT: +0.85V_PS_GTR_AVCC
EN_VCCINT	inout	H8	5	weak pull-up	3.3V LVCMOS	2mA (default)	enable signal for LTM4700 (U20) RUN0/1: EN_VCCINT PGOOD0/1: PG_VCCINT
EN_2V3	out	G13	5	--	3.3V LVTTL	8mA (default)	enable signal for TPS82130 (U45) EN: EN_+2.3V PG: PG_+2.3V VOUT: +2.3V

Functional Description

JTAG

JTAG access to Intel MAX 10 is available through B2B connector J2.

JTAG Signal	B2B Connector
JTAGEN	Pulled Up
TCK_MAX10	J2B- D56
TDI_MAX10	J2B- D59
TDO_MAX10	J2B- D58
TMS_MAX10	J2B- D57

Power

All power regulators are controlled by the power sequencer core from Intel. It enables and discharges the power regulators and monitors the power good signals. As the power good inputs of the power sequencer are very sensitive, all power good inputs were debounced. https://github.com/intel/multi_power_sequencer

The power-up sequence corresponds to AMD's recommendations and is shown in the table below:

Power Group	Power enable signal (CPLD output signal)	Power good signal (CPLD input signal)	Sequencer Delay¹ (PG to next OE)	Qualification Window² (OE to PG)	Notes
0	--	EN_SOM	10µs	200ms
1	EN_VCCINT	PG_VCCINT	10µs	200ms	--
	EN_2V3	PG_2V3			--
	EN_3V3_SW	PG_3V3_SW			+3.3V_SW output signal from U52
2	EN_1V8	PG_1V8	10µs	200ms	--
	EN_1V8_AUX	PG_1V8_AUX			--
	EN_1V8_PS_AUX	--			--
	EN_1V2_PS_PLL	--			--
	EN_0V9_GTH_AVCC	PG_0V9_GTH_AVCC			--
	EN_0V9_GTY_AVCC	PG_0V9_GTY_AVCC			--
	EN_1V8_VCC_ADC	--			--
3	EN_1V2_PS_DDR	PG_1V2_PS_DDR	10µs	200ms	--
	EN_1V2_PL_DDR	PG_1V2_PL_DDR			--
	EN_2V5_PL_DDR	PG_2V5_PL_DDR			--
	EN_2V5_PS_DDR	PG_2V5_PS_DDR			--
	EN_1V2_GTH_AVTT	PG_1V2_GTH_AVTT			--
	EN_1V2_GTY_AVTT	PG_1V2_GTY_AVTT			--
4	EN_VTT_PS_DDR	--	10µs	200ms	--
	EN_0V85_PS_GTR_AVCC	PG_0V85_PS_GTR_AVCC			--
	EN_VTT_PL_DDR	--			--
	EN_1V8_GTH_AUX	--			--
	EN_1V8_GTY_AUX	--			--
5	EN_1V8_PS_GTR_AVTT	PG_1V8_PS_GTR_AVTT	10µs	200ms	--
6	PG_SOM	--	0µs	200ms	--

1. Defines the delay from when the master enable is asserted before output enable is asserted, or from when Power Good is asserted until the next rail or group's output enable is asserted.
2. Defines the qualification window for which Power Good must be asserted, after output enable is asserted.

JTAG UART

As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.

The command "nios2-terminal.exe" in the NIOS II command shell is used to output the CPLD Firmware and PCB revision. In case of power problems the power enable and power good signals will be displayed additionally.

Expand

title	example normal operation

Image Added

Expand

title	example power enable and power good signals

Image Added

I2C interface

The CPLD firmware consists of an I2C slave to Avalon MM master bridge Intel FPGA IP, allowing the CPLD registers to be accessed. The device address in the firmware is 0x55, CPLD registers can be accessed via the i2c interface, e.g. in the Linux console with

i2cget -y 1 0x55 <Index> (for reading) or
i2cset -y 1 0x55 <Index> <Value> (for writing)

The following table shows the register map for the CPLD interface :

Index	Byte	Register Name	Read/Write	Description	Default
0x0	[7:0]	SC_REVISION	R	CPLD Firmware Revision	0x3
0x1	[7:0]	PCB_REVISION	R	PCB Revision	0x2
0x6	[7:0]	pwr_en	R	Status of Power Groups Bit 0: Power Group 0 Enable Power Sequencer Bit 1: Power Group 1 EN_VCCINT EN_2V3 EN_3V3_SW Bit 2: Power Group 2 EN_1V8 EN_1V8_AUX EN_1V8_PS_AUX EN_1V2_PS_PLL EN_0V9_GTH_AVCC EN_0V9_GTY_AVCC EN_1V8_VCC_ADC Bit 3: Power Group 3 EN_1V2_PS_DDR EN_1V2_PL_DDR EN_2V5_PL_DDR EN_2V5_PS_DDR EN_1V2_GTH_AVTT EN_1V2_GTY_AVTT Bit 4: Power Group 4 EN_VTT_PS_DDR EN_0V85_PS_GTR_AVCC EN_VTT_PL_DDR EN_1V8_GTH_AUX EN_1V8_GTY_AUX Bit 5: Power Group 5 EN_1V8_PS_GTR_AVTT Bit 6: Power Group 6 PG_SOM Bit 7: not used	0x7F
0x8	[7:0]	power_good_in[7:0]	R	Status of Power Good Signals Bit 0: EN_SOM Bit 1: PG_VCCINT Bit 2: PG_2V3 Bit 3: PG_3V3_SW Bit 4: PG_1V8 Bit 5: PG_1V8_AUX Bit 6: PG_0V9_GTH_AVCC Bit 7: PG_0V9_GTY_AVCC	0xFF
0x9	[7:0]	power_good_in[15:8]	R	Status of Power Good Signals Bit 0: PG_1V2_PS_DDR Bit 1: PG_1V2_PL_DDR Bit 2: PG_2V5_PL_DDR Bit 3: PG_2V5_PS_DDR Bit 4: PG_1V2_GTH_AVTT Bit 5: PG_1V2_GTY_AVTT Bit 6: PG_0V85_PS_GTR_AVCC Bit 7: PG_1V8_PS_GTR_AVTT	0xFF
0xA	[7:0]	seq_nfault	R	Status of Power Sequencer (Active Low)	0x1
0xE	[7:0]	pwr_usb_ena	R/W	Enables/Disables output signal 'SC_EXT_2' Is used for USB enable voltage in TEBT0865	0x0 (0x1 in Reference Design)

Reference Design

In the reference design, the I2C interface in u-boot is used to read out the CPLD and PCB revision as well as to switch on the output signal 'SC_EXT_2' for the USB voltage on the carrier board TEBT0865. These information will be displayed while booting the reference design as shown:

Scroll Title

title-alignment	center
title	U-boot snippet reference design

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Reset

The reset signals ‘MR’ and ‘nRST_SYS’ will be released after power group 6 has been activated.

Appx. A: Change History

Revision Changes

REV02 to REV03
- changed top design from block design to text design
- added power sequencer
- added debouncing for power good signals
- added jtag_uart
- added i2c interface
- added release for reset (MR and nRST_SYS)
- added logic for SC_EXT_2
  - enable/disable USB power for TEBT0865 via I2C
  - default: disabled
- update constraining

Boot modeBOOT_MODE = <boot mode>

The following boot modes can displayed:
- eMMC (0)
- JTAG (1)
- QSPI (2)
- SD Card (3)

The CPLD revision, boot mode and other informations will be displayed while booting as shown:

Scroll Title

title-alignment	center
title	All information while booting

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If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:

Scroll Title

title-alignment	center
title	Message while booting if CPLD firmware version is old for PCB REV04

Image Removed

Appx. A: Change History

For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD

Revision Changes

REV02 to REV03
- changed top design from block design to text design
REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Firmware Release

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

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	current-version
prefix	v.

REV03

REV02

modified-user

Page info

modified-user

infoType	Modified by
type	Flat

Update Change History

SC-PGM-TE0865-02_SC0865-03_20240918.zip

2024-09-18

v.38

REV03

REV02

Manuela Strücker

Documentation initial release

All

Page info

	modified-users
	modified-users

Appx. B: Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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<style> .wiki-content .columnLayout .cell.aside { width: 0%; }</style>

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Trenz Electronic Documentation

Versions Compared

Old Version 14

New Version Current

Key

Overview

Feature Summary

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

Power

JTAG UART

I2C interface

NOSEQ pin

Access to CPLD Registers

Functional Description

JTAG

Power

JTAG UART

I2C interface

Reference Design

Reset

Appx. A: Change History

Revision Changes

Revision Changes

Document Change History

Appx. B: Legal Notices

Table of contents