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Table of contents
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The "normal" Vivado project will be generated in the subfolder "/vivado/" after executing scripts (YouTube: TE0720 Project Creation).
There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects.
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Directory structure
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- XILINXGIT_DEVICETREE: can be used to generate device tree with SDK
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- XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES: additinal micro uboot messages (Zynq)
- XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ: additinal micro uboot programming speed(Zynq)
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Linux Command Files
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Settings for the other *.cmd files. Following Settings are avaliable:
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(optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".
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(MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
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Make a Backup from your Project in <design_name>/backup/
Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported.
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Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state.
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Design Environment: Usage
Reference-Design: Getting Started
- Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
(optional) Install Xilinx Vivado LabTools (Lab Edition) - Configure the reference-design:
1. Open “design_basic_settings.cmd” with a text-editor:
a. Set correct Xilinx Environment:
@set XILDIR=C:/Xilinx
@set VIVADO_VERSION=2018.2
Program settings will be search in :
%XILDIR%/VIVADO/%VIVADO_VERSION%/
%XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
%XILDIR%/SDK/%VIVADO_VERSION%/
Example directory: c:/Xilinx/Vivado/2018.2/
Attention: Scripts are supported only with predefined Vivado Version!
b. Set the correct module part-number:
@set PARTNUMBER=x
You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
c. Set Application name (for programming with batch-files only):
@set SWAPP=NA
NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
<app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> - Create all prebuilt files in one step:
2. Run “design_run_project_batchmode.cmd” - (optional to Step 2) Create all prebuilt files in single steps:
3. Run “vivado_create_project_guimode.cmd”:
A Vivado Project will be create and open in ./vivado
4. Type “TE::hw_build_design” on Vivado TCL-Console:
Run Synthese, Implement and create Bitfile and optional MCSfile
5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
Create all Software Applications from <design_name>/sw_lib/apps_list.csv
6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
Create a SDK Project in <design_name>/workspace/sdk
Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin):
Run “program_flash_binfile.cmd”
9. (optional) FPGA-Device Flash Programming (*.mcs):
Run “program_flash_mcsfile.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
13. (optional) FPGA-Device Flash Programming (*.mcs):
Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
14. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
Basic Design Settings
Project Configuration
- Unzip project files
- Rename basefolder (basefolder name is used as project name)
- Edit design_basic_settings.cmd
- Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
- Select the correct board part number for your PCB (See: Windows Command Files → design_basic_settings.cmd)
- Other settings are optional (See: Windows Command Files → design_basic_settings.cmd)
- Excecute vivado_create_project_guimode.cmd or vivado_create_project_batchmode.cmd to generate a vivado project with the predefined Block Design from the Block Design folder
- Open Vivado with vivado_open_existing_project_guimode.cmd (if you use vivado_create_project_guimode.cmd on step 4, you didn't need this)
- Open the Block Design and create your own design inside this Block Design.
- Backup your Block Design as tcl-script: Type "TE::hw_blockdesign_export_tcl" on Vivado Tcl Console. The old one will be overwritten.
- Build your Design...
Initialise TE-scripts on Vivado/LabTools
- Variant 1 (recommended):
- Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
- Variant 2:
- Create your own Initialisation Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push
- Type Name ex.: Init Scripts
- Press Enter
- Select Run command and insert:
- for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
- for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
- Press Enter
- A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
- Create your own Initialisation Button on the Vivado GUI:
- Variant 3:
- Reinitialise Script on Vivado TCL-Console:
- Type: source ../scripts/reinitialise_all.tcl
- Type: source ../scripts/reinitialise_all.tcl
- Reinitialise Script on Vivado TCL-Console:
Use predefined TE-Script functions
- Variant 1 (recommended):
- Typ function on Vivado TCL Console, ex.: TE::help
- TE::help
- Show all predefined TE-Script functions.
- TE:<functionname> -help
- Show short description of this function.
- Attention: If -help argument is set, all other args will be ignored.
- Variant 2:
- Create your own function Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push +
- Type Name ex.: Run SDK
- Press Enter
- Select Run command and insert function:
- Variante 1 (no Vivado request window for args):
- insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
- Variant 2 (Vivado request window for args):
- insert function, ex.:TE::sw_program_zynq
- Press Define Args...
- For every arg:
- Push
- Typ Name, Comment, Default Value and set optional
- Press Enter
- Example for args:
- Push
- Index, Key Name, -swapp,
- Push
- Appname, Arg, hello_world,
- Push
- Push
- Variante 1 (no Vivado request window for args):
- Press Enter
- A new Button is shown on the Vivado Gui.
- Create your own function Button on the Vivado GUI:
Hardware Design
Board Part Files
See also TE Board Part Files
Structure Board Parts
Board Parts are located on subfolder "board_files", with the name of the special board. Revisions are splitt in the subfolder of the board part <boardpart_name><version>
Every Version of a Board Parts consists of four files:
- board.xml
- part0_pins.xml
- preset.xml
- picture.jpg or picture.png
Board Part Carrier Extension
Board Part Carrier Extensions are a TCL-Scripts, which can be sourced in Vivado Block Design. Thy are used with TE-Scripts only. It contains additional settings of PS-System for special carrier-board, if no special Board part file exists.
Board Part Carrier Extensions are located on subfolder "board_files/carrier_extension/" with file name *_preset.tcl.
Use Reference Designs or Vivado TCL-Console(TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation"
Board Part CSV Description
Board Part csv file is used for TE-Scripts only.
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"<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32
Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build.
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Block Design Conventions
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Recommended BD-Names (currently importend for some TE-Scripts):
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Program flash with the given swapp from the prebuilt folder ("<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"). | ||
| TE::pr_putty | [-available_com] [-com] [-speed] [-help] | Show available COM ports and open automatically the UART COM port, in case only one is selectable Important:
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| Utilities | ||
| TE::util_zip_project | [-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help] | Make a Backup from your Project in "<project folder>/backup/" Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported. |
| TE::util_editor | [-file <arg>] [-help] | open file with editor which is set on "TE_EDITOR" Enviroment variable |
| TE::util_terminal | [-help] | linux only. open new terminal |
| TE::util_package_length | [-help] | Export Package IO length information to *.csv on the doc folder |
| TE::util_svn | [-status] [-update] [-add <arg>] [-remove <arg>] [-commit <arg>] [-commit\] [-help] | start svn commands on the current project(project must be under SVN Version) On Win OS: Need Tortouise SVN with command line tools installation On Linux: Need subversion installed, for example sudo apt-get install subversion -y |
| Beta Test (Advanced usage only!) | ||
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| TE::ADV::beta_hw_remove_board_part | [-permanent] [-help] | Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported. |
| TE::ADV::beta_hw_export_rtl_ip | \[-help\] | Save IPs used on rtl designs as *.xci in "<project folder>hdl/xci". If sub folder "<board_file_shortname>" is defined this will be saved there. |
| TE::ADV::beta_hw_create_board_part | \[-series <arg>\] \[-all\] \[-preset\] \[-existing_ps\] \[-help\] | create PS or preset.xml PS settings from external tcl scripts |
| TE::ADV::beta_hw_export_binary | \[-mode <arg>\] \[-app <arg>\] \[-folder <arg>\] \[-all\] \[-help\] | export prebuilt files to an given folder (based from project folder). Special folder is used, if empty |
Design Environment: Usage
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Reference-Design: Getting Started
- Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
(optional) Install Xilinx Vivado LabTools (Lab Edition) - Automatically configuration of the reference-designs (only with 2018.3 scripts and newer):
- Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
- select "module selection guide" and follow instructions.
- "design_basic_settings.cmd" will be configured over this menu
- select "module selection guide" and follow instructions.
- Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
- (optional for 18.3 or newer) Manual Configure the reference-design (Note: batch/bash files works only in the basefolder of the project, use _create_*_setup.cmd/sh or copy manually ):
1. Open “design_basic_settings.cmd” with a text-editor:
a. Set correct Xilinx Environment:
@set XILDIR=C:/Xilinx
@set VIVADO_VERSION=2023.2
Program settings will be search in :
%XILDIR%/VIVADO/%VIVADO_VERSION%/
%XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
%XILDIR%/Vitis/%VIVADO_VERSION%/
Example directory: c:/Xilinx/Vivado/2023.2/
Attention: Scripts are supported only with predefined Vivado Version!
b. Set the correct module part-number:
@set PARTNUMBER=x
You found the available Module Numbers in "<project folder>/board_files/<board_series>_board_files.csv"
c. Set Application name (for programming with batch-files only):
@set SWAPP=NA
NA (No Software Project) used *.bit or *.mcs from "<project folder>/prebuilt/hardware/<board_file_shortname>"
<app_name> (Software Project) used *.bit or *.mcs or *.bin from "<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>" - Create all prebuilt files in one step:
2. Run “design_run_project_batchmode.cmd” - (optional to Step 2) Create all prebuilt files in single steps:
3. Run “vivado_create_project_guimode.cmd”:
A Vivado Project will be create and open in ./vivado
4. Type “TE::hw_build_design” on Vivado TCL-Console:
Run synthesis, Implement and create Bitfile and optional MCSfile
5. Type “TE::sw_run_vitis -all -no_gui” on Vivado TCL-Console:
Create all Software Applications from "<project folder>/sw_lib/apps_list.csv"
6. (optional to Step 5) Type “TE::sw_run_vitis ” on Vivado TCL-Console:
Create a SDK Project in "<project folder>/workspace/sdk"
Include Hardware-Definition-File, Bit-file and local Software-libraries from "<project folder>/sw_lib/sw_apps" Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin) or FPGA-Device Flash Programming (*.mcs):
Run “program_flash.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash -swap <app_name>” on Vivado TCL-Console
Used .bin(Zynq)/.mcs(native FPGA) "<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"
13. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from "<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"
Basic Design Settings
Initialise TE-scripts on Vivado/LabTools
- Variant 1 (recommended):
- Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
- Variant 2:
- Create your own Initialisation Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push
- Type Name ex.: Init Scripts
- Press Enter
- Select Run command and insert:
- for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
- for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
- Press Enter
- A new Button is shown on the Vivado GUI: All Scripts are reinitialised, if you press this Button.
- Create your own Initialisation Button on the Vivado GUI:
- Variant 3:
- Reinitialise Script on Vivado TCL-Console:
- Type: source ../scripts/reinitialise_all.tcl
- Type: source ../scripts/reinitialise_all.tcl
- Reinitialise Script on Vivado TCL-Console:
Use predefined TE-Script functions
- Variant 1 (recommended):
- Type function on Vivado TCL Console, ex.: TE::help
- TE::help
- Show all predefined TE-Script functions.
- TE:<function_name> -help
- Show short description of this function.
- Attention: If -help argument is set, all other args will be ignored.
- Variant 2:
- Create your own function Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push +
- Type Name ex.: Run SDK
- Press Enter
- Select Run command and insert function:
- Variante 1 (no Vivado request window for args):
- insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
- Variant 2 (Vivado request window for args):
- insert function, ex.:TE::sw_program_zynq
- Press Define Args...
- For every arg:
- Push
- Type Name, Comment, Default Value and set optional
- Press Enter
- Example for args:
- Push
- Index, Key Name, -swapp,
- Push
- Appname, Arg, hello_world,
- Push
- Push
- Variante 1 (no Vivado request window for args):
- Press Enter
- A new Button is shown on the Vivado GUI.
- Create your own function Button on the Vivado GUI:
Environment Variables
Local
| Files | Note |
|---|---|
| <project folder>/design_basic_settings.cmd/sh | General local variables for project generation |
| <project folder>/settings/design_settings.tcl | Design setting like Device Filter, UART Speed and Port |
| <project folder>/settings/development_setting.tcl | Development settings which can manipulate execution steps |
Global
| Name | Value | Note |
|---|---|---|
| TE_SERIAL_PS | <path> | Internal usage only |
| TE_COM | <path> | path to putty, in case it's not installed global |
| TE_TIMEOUT | <time> | timeout for jobs, unit in minutes, def 120 |
| TE_RUNNING_JOBS | <count> | max jobs (depends on available CPUs) which can be started by Vivado, default 4 |
| TE_WSL_USAGE | 1/0 | 1 use Windows programs for some external processes |
| TE_GUI_DISABLED | 1/0 |
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| TE_EDITOR | <name> | Text Editor which should be started for some TE functions |
| TE_PLX_SSTATE_CACHE_DOWNLOAD | <path> | Local version of SSTATE, file avialable on the download area from Xilinx petalinux, example: TE_PLX_SSTATE_CACHE_DOWNLOAD="~/design/sstate-cache/downloads_2023.2/downloads" |
| PLX_SSTATE_CACHE_AARCH64 | <path> | Local version of SSTATE for U+ Zynq and Versal, file avialable on the download area from Xilinx petalinux, example: TE_PLX_SSTATE_CACHE_DOWNLOAD="~/design/sstate-cache/downloads_2023.2/downloads" |
| PLX_SSTATE_CACHE_ARM | <path> | Local version of SSTATE for Zynq 7000, file avialable on the download area from Xilinx petalinux, example: PLX_SSTATE_CACHE_ARM="~/design/sstate-cache/sstate_arm_2023.2/arm" |
| PLX_SSTATE_CACHE_MB_FULL | <path> | Local version of SSTATE for Microblaze, file avialable on the download area from Xilinx petalinux, example: PLX_SSTATE_CACHE_ARM="~/design/sstate-cache/sstate_mb_full_2023.2/mb_full" |
| PLX_SSTATE_CACHE_MB_LITE | <path> | currently not supported |
Hardware Design
Board Part Files
More details see TE Board Part Files
Structure Board Parts
Board Parts are located on subfolder "board_files", with the name of the special board. Revisions are split in the subfolder of the board part <boardpart_name><version>
Every Version of a Board Parts consists of four files:
- board.xml
- part0_pins.xml
- preset.xml
- picture.jpg or picture.png
Board Part or Design Extension
Board Part Extensions are TCL-Scripts, which can be sourced in Vivado Block Design. Thy are usable with TE-Scripts only. It contains additional settings of PS-settings or special carrier-board design changes.
Use Reference Designs or Vivado TCL-Console (TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation"
Possible:
- Board Part PS settings are located on subfolder "board_files/preset_extension/" with file name *_preset.tcl.
- Design modifications are located on subfolder "board_files/bd_mod/" with file name *_bd.tcl.
Board Part CSV Description
Board Part csv file is used for TE-Scripts only.
| Name | Description | Value |
|---|---|---|
| ID | ID to identify the board variant of the module series, used in TE-Scripts | Number, should be unique in csv list |
| PRODID | Product ID | Product Name |
| PARTNAME | FPGA Part Name, used in Vivado and TE-Scripts | Part Name, which is available in Vivado, ex. xc7z045ffg900-2 |
| BOARDNAME | Board Part Name, used in Vivado and TE-Scripts | set Board Part Name or "NA", which is available in Vivado, NA is not defined to run without board part and board part ex. trenz.biz:te0782-02-45:part0:1.0 |
| SHORTNAME | Subdirectory name, used for multi board projects to get correct sources and save prebuilt data | name to save prebuilt files or search for sources |
| ZYNQFLASHTYP | Flash type used for programming Zynq-Devices via SDK-Programming Tools (program_flash) | "qspi_single" or "NA", NA is not defined |
| FPGAFLASHTYP | Flash type used for programming Devices via Vivado/LabTools | "<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32 Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build. For Zynq and ZynqMO only Flash name is necessary |
| PCB_REV | Supported PCB Revision | "<supported PCB Revision>|<supported PCB Revision>", for ex. "REV02" or "REV03|REV02" |
| DDR_SIZE | Size of Module DDR | use GB or MB, for ex. "2GB" or "512MB" or "NA" if not available |
| FLASH_SIZE | Size of Module Flash | use MB, for ex. "64MB" or "NA" if not available |
| EMMC_SIZE | Size of Module EMMC | use GB or MB, for ex. "4GB" or "NA" if not available |
| OTHERS | Other module relevant changes to distinguish assembly variants | |
| NOTES | Additional Notes | |
| DESIGN | Specify the allowed variants for different designs. | see also <design folder>\settings\design_settings.tcl |
| CONFIG_SW_EXTPLL | Optional parameter to support different PLL Versions which can be programmed Replace all files with the same file name on sw_lib folder with the specified one | relativ path to the source file, for example "./misc/PLL/SI5345_D/te_Si5345-Registers.h" |
Block Design Conventions
- Only one Block-Design per project is supported
Recommended BD-Names (currently importend for some TE-Scripts):
Name Description zsys Identify project as Zynq Project with processor system (longer name with *zsys* are supported too) zusys Identify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too) msys Identify project as Microblaze Project with processor system (longer name with *msys* are supported too) fsys Identify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too) - Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help
XDC Conventions
- All *.xdc from <project folder>/constrains/ are load into the vivado project on project creation.
Attention: If subfolder <project folder>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module! Recommended XDC-Names (used for Vivado XDC-options):
Property Name part Description Set Processing Order *_e_* set to early *_l_* set to late set to normal Set Used In *_s_* used in synthesis only *_i_* used in implement only used in both, synthesis and implement
Backup Block Design as TCL-File
- Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <project folder>/block_design/
It will be saved as *_bd.tcl
Attention: If subfolder <project folder>/block_design/<board_file_shortname> or <project folder>/block_design/PCB Revision> is defined, it will be saved there!
Only one *.tcl file should be in the backup folder respectively the subfolder <board_file_shortname>
Microblaze Firmware
- Microblaze Firmware (*.elf) can be add to the source folder <project folder>/firmware/<Microblaze IP Instance>.
- For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.
Software Design
Vitis: Generate predefined software from libraries
- To generate predefined software from libraries, run "TE::sw_run_vitis -all -no_gui" on Vivado TCL-Console
- All programs in in <project folder>/sw_lib/apps_list.csv are generated automaticity
- Supported are local application libraries from <project folder>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app
VITIS: Create user software project
- To start SDK project, run "TE::sw_run_vitis" on Vivado TCL-Console or run "TE::sw_run_vitis -workspace_only" on Vivado TCL-Console
Include Hardware-Definition-File (XSA), Bit-file and local Software-libraries from "<project folder>/sw_lib/sw_apps" - To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type "TE::sw_run_vitis -prebuilt_xsa <board_number>" on Vivado-TCL-Console
- To open an existing SDK-project without update HDF-Data, type "TE::sw_run_vitis -gui_only" on Vivado-TCL-Console
Advanced Usage
Attention not all features of the TE-Scripts are supported in the advanced usage!
User defined board part csv file
To modify current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.
See Chapter Board Part Files for more information.
User defined Settings
- Vivado settings:
- Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<project folder>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
- Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<project folder>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
- Script settings:
- Additional script settings (only some predefined variables) can be saved as a user defined file "<project folder>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
- Design settings:
- Additional script settings (only some predefined variables) can be saved as a user defined file "<project folder>/settings/design_settings.tcl". This file will be loaded automatically on script initialisation.
- ZIP ignore list:
- Files which should not be added in the backup file can be can be defined in this file: "<project folder>/settings/zip_ignore_list.tcl". This file will be loaded automatically on script initialisation.
- SDSOC settings:
- SDSOC settings will are deposited on the following folder: "<project folder>/settings/sdsoc"
User defined TCL Script
TCL Files from "<project folder>/settings/usr" will be load automatically on script initialisation.
SDSOC-Template
SDSOC description and files to generate SDSoC project are deposited on the following folder: "<project folder>/settings/sdsoc"
HDL-Design
HDL files can be saved in the subfolder "<project folder>/hdl/" as single files or <project folder>/hdl/folder/ and all subfolders or "<project folder>/hdl/<shortname>" and all subfolders of "<project folder>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv. A own top-file must be specified with the name "<project folder>_top.v" or "<project folder>_top.vhd".
To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for synthesis only.
IP-cores (*.xci). can be saved in the subfolder "<project folder>/hdl/xci" or "<project folder>/hdl/xci/<shortname>". They will be loaded automatically on project creation.
IP -TCL description (*_preset.tcl). can be saved in the subfolder "<project folder>/hdl/tcl" or "<project folder>/hdl/tcl/<shortname>". They will be loaded automatically on project creation.
- *_preset.tcl must include
- TCL part for IP creation: create_ip -name ...
- TCL part for IP configuration: set_property -dict...
- TCL part for IP target generation: generate_target {instantiation_template} .....
- TCL part for IP creation: create_ip -name ...
Checklist / Troubleshoot
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- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Are you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Win OS only: Use short path name, OS allows only 256 characters in normal path.
- Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be display: /bin/sh -> bash. Access rights can be changed with "chmod"
- Are space character on the project path? Sometimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <project folder>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisation problem) and the scripts cancelled. Please try again.
- If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<project folder>/v_log/vivado.log)
References
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- Vivado Design Suite User Guide - Getting Started (UG910)
- Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
- Vivado Design Suite User Guide - I/O and Clock Planning (UG899)
- Vivado Design Suite User Guide - Programming and Debugging (UG908)
- Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
- SDSoC Environment User Guide - Getting Started (UG1028)
- SDSoC Environment - User Guide (UG1027)
- SDSoC Environment User Guide - Platforms and Libraries (UG1146)
Document Change History
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To get content of older revision got to "Change History" of this page and select older revision number.
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<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview, Vivado Version(or update)to the empty row
3.Update Metadate =Page Information Macro Preview+1
--> |
| Date | Revision | Vivado Version | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| 2022.2 |
| working in process | ||||||||||||||||||||||
2023-08-15 | v.176 | 2022.2 | John Hartfiel | Last Vivado 2022.2 supported project delivery version | ||||||||||||||||||||||
| 2023-02-06 | v.171 | 2021.2 | John Hartfiel | Last Vivado 2021.2 supported project delivery version | ||||||||||||||||||||||
| 2021-05-06 | v.162 | 2020.2 | Manuela Strücker | Last Vivado 2020.2 supported project delivery version | ||||||||||||||||||||||
| 2020-11-26 | v.157 | 2019.2 | John Hartfiel | Last Vivado 2019.2 supported project delivery version | ||||||||||||||||||||||
| 2019-12-18 | v.148 | 2018.2 | John Hartfiel | Last Vivado 2018.3 supported project delivery version | ||||||||||||||||||||||
| --- | --- | 2018.2 | John Hartfiel | Last Vivado 2018.2 supported project delivery version
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2019-07-10 | v.142 | 2017.4 | John Hartfiel | Last Vivado 2017.4 |
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XDC Conventions
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Recommended XDC-Names (used for Vivado XDC-options):
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Backup Block Design as TCL-File
- Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
It will be saved as *_bd.tcl
Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>
Microblaze Firmeware
- Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance> or <design_name>/firmware/<BD hierarchie>/<Microblaze IP Instance>.
- For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.
Software Design
HSI: Generate predefined software from libraries
- To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
- All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
- Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app
SDK: Create user software project
- To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps - To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
- To open an existing SDK-project without update HDF-Data, type "TE::sw_run_sdk -open_only" on Vivado-TCL-Console
Advanced Usage
Attention not all features of the TE-Scripts are supported in the advanced usage!
User defined board part csv file
To modifiy current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.
See Chapter Board Part Files for more information.
User defined Settings
Vivado settings:
Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
Script settings:
Additional script settings (only some predefined variables) can be saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
ZIP ignore list:
Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.
SDSOC settings:
SDSOC settings will are deposited on the following folder: "<design_name>/settings/sdsoc"
User defined TCL Script
TCL Files from "<design_name>/settings/usr" will be load automaticaly on script initialisation.
SDSOC-Template
SDSOC description and files to generate SDSoC project are deposited on the following folder: "<design_name>/settings/sdsoc"
HDL-Design
HDL files can be saved in the subfolder "<design_name>/hdl/" as single files or <design_name>/hdl/folder/ and all subfolders or "<design_name>/hdl/<shortname>" and all subfolders of "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv. A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".
To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for synthese only.
RTL-IP-cores (*.xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.
Checklist / Troubleshoot
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Win OS only: Use short path name, OS allows only 256 characters in normal path.
- Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be desplay: /bin/sh -> bash. Access rights can be changed with "chmod"
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation problem) and the scripts canceled. Please try again.
- If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
References
- Vivado Design Suite User Guide - Getting Started (UG910)
- Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
- Vivado Design Suite User Guide - I/O and Clock Planning (UG899)
- Vivado Design Suite User Guide - Programming and Debugging (UG908)
- Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
- SDSoC Environment User Guide - Getting Started (UG1028)
- SDSoC Environment - User Guide (UG1027)
- SDSoC Environment User Guide - Platforms and Libraries (UG1146)
Document Change History
To get content of older revision got to "Change History" of this page and select older revision number.
| HTML |
|---|
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview, Vivado Version(or update)to the empty row
3.Update Metadate =Page Information Macro Preview+1
--> |
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- 2018.2 Work in progress
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