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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Project+Delivery+-+Xilinx+devices |
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The most Trenz Electronic FPGA Reference Designs are TCL-script based project.
The "normal" Vivado project will be generated in the subfolder "/vivado/" after executing scripts (YouTube: TE0720 Project Creation).
There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects - TE Reference Design.
Since 2018.3 special "Module Selection Guide" is included into "_create_win_setup.cmd" and "_create_linux_setup.sh"
For
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manual configuration or addition command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS. If you use our prepared batch files for project creation do the following steps:
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See Reference Design: Getting Started for more details.
If you need our Board Part files only, see Board Part Installation.
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For Problems, please check Checklist / Troubleshoot at first. |
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Description | PCB Name | Project Name+(opt. Variant) | supported VIVADO Version | Build Version and Date | ||||
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Example: |
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te0720 | - | -test_board(_noprebuilt) | - | vivado_ |
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2023. |
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2 | - | build_ |
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1_ |
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20231124235959 | .zip |
Type or File | Version | Note |
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Vivado Design Suite |
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2023. |
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2 | |
Trenz Project Scripts |
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2023.2.3 |
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Trenz <board_series>_board_files.csv | 1.4 | |
Trenz apps_list.csv | 2. |
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Trenz zip_ignore_list.csv | 1.0 | |
Trenz mod_bd.csv |
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1.1 | internal usage only | |
Trenz prod_cfg_list.csv | 1.0 | internal usage only |
Trenz zip.info | 1.0 |
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File or Directory | Type | Description |
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<project folder> | base directory | Base directory with predefined batch files (*.cmd) to generate or open VIVADO-Project |
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<project folder>/block_design/ | source | Script to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_ |
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shortname> with Board Part specific Block Design (*_bd.tcl). |
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<project folder>/board_files/ | source | Local board part files repository and a list of available board part |
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files (<board_series>_board_files.csv) |
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<project folder>/board_files/carrier_extension | source | (Optional) Additional TCL-Scripts to extend Board Part PS-Preset with carrier board specific settings. |
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<project folder>/console | source | folder with different console command files. Use _create_win_setup.cmd or _create_linux_setup.sh to generate files on top folder. |
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<project folder>/constraints/ | source | Project constrains (*.xdc). Some board part designs used subfolder <board_file_ |
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shortname> with additional constrains (*.xdc) |
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<project folder>/doc/ | source | Documentation |
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<project folder>/hdl/ | source | HDL-File and XCI-Files. Advanced usage only! |
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<project folder>/firmware/ | source | ELF-File Location for MicroBlaze Firmware. |
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Additional sub folder is used for MicroBlaze identification. |
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<project folder>/ip_lib/ | source | Local Vivado IP repository |
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<project folder>/misc/ | source | (Optional) Directory with additional sources |
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<project folder>/prebuilt/ | prebuilt | Contains a readme with location information of different assembly variants |
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<project folder>/prebuilt/boot_images/ | prebuilt | Directory with prebuilt boot images (*.bin) and configuration files (*.bif) |
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for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name> |
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<project folder>/prebuilt/hardware/ | prebuilt | Directory with prebuilt hardware sources (*.bit, * |
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xsa, *.mcs) and reports included in subfolders: default or <board_file_shortname> |
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<project folder>/prebuilt/software/ | prebuilt | (Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name> |
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<project folder>/prebuilt/os/ | prebuilt | (Optional) Directory with predefined OS images included in |
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subfolders "<os_name>/<board_file_shortname>" or "<os_name>/ |
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<ddr size>" |
<project folder> |
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/scripts/ | source | TCL scripts to build a project |
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<project folder>/settings/ | source | (Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings |
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<project folder>/software/ | source | (Optional) Directory with additional software |
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<project folder>/os/ | source | (Optional) Directory with additional os sources in in |
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subfolders "<os_name>" |
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<project folder>/sw_lib/ | source | (Optional) Directory with local |
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Vitis software IP repository and a list of available software (apps_list.csv) |
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<project folder>/v_log/ | generated | (Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be |
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written into the vivado working directory) |
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<project folder>/vivado/ | work, generated | (Temporary) Working directory where Vivado project is created. Vivado project file is |
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<project folder>.xpr |
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<project folder>/vivado_lab/ | work, generated | (Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is |
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<project folder>.lpr |
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obsolete | (Optional/Temporary) Directory where hsi project is created |
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<project folder>/workspace/sdk | work, generated | (Optional) Directory where |
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Vitis project is created |
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<project folder>/tmp/ | work, generated | (Optional) Directory for some tasks |
<project folder>/_binaries_<articlenumber> | generated | export directory for binaries (run "_create_win_setup.cmd" and follow instructions) |
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obsolete | (Optional) Directory where SDSOC project is created |
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<project folder>/backup/ | generated | (Optional) Directory for project backups |
Command files will be generated with "_create_win_setup.cmd" on
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Windows and "_create_linux_setup.sh" on Linux OS. Linux shell files are currently not available for this release.
File Name | Status | Description |
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Design + Settings | ||
_create_win_setup.cmd | available | Use to create bash files. With 2018.3 and newer also "Module Selection Guide" is included |
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and with 2023.2 prebuilt export for the selected variant |
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use_virtual_drive.cmd | available | (Option) Create virtual drive for project execution. See Xilinx AR#52787 |
design_basic_settings.cmd | available | Settings for the other *.cmd files. Following Settings are |
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available:
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design_clear_design_folders.cmd | available | (optional) |
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Attention: Delete " |
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<project folder>/v_log/", " |
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<project folder>/vivado/", " |
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<project folder>/vivado_lab/", " |
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<project folder>/sdsoc/", and " |
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<project folder>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files | ||
design_run_project_batchmode.cmd | available | (optional) |
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Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. |
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Delete "<project folder>/vivado/", and " |
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<project folder>/workspace/ |
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sdk/" directory with related documents before Project will created. | ||
Hardware Design | ||
vivado_create_project_guimode.cmd | available | Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete " |
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<project folder>/vivado/", and " |
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<project folder>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. | ||
vivado_create_project_batchmode.cmd | available | (optional) |
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Create Project with setting from "design_basic_settings.cmd" and source folders. |
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Delete "<project folder>/vivado/", and " |
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<project folder>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. | ||
vivado_open_existing_project_guimode.cmd | available | Opens an existing Project " |
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<project folder>/vivado/<design_name>.xpr" and restore Script-Variables. | ||
Software Design | ||
sdk_create_prebuilt_project_guimode.cmd | available | (optional) Create |
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Vitis project with hardware definition file from prebuild folder. It used the *. |
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xsa from: |
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"<project folder>/prebuilt/hardware/<board_file_shortname>/". Set "<board_file_shortname> |
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" and "<app_name>" in "design_basic_settings.cmd". | ||
Programming | ||
program_flash |
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.cmd | available | (optional) |
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Programming Flash Memory via JTAG with specified |
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*.bin |
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(Zynq devices) or *.mcs (native FPGA). Used LabTools Programmer (Vivado or LabTools only |
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. Default, it used the boot.bin from: |
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"<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>". Settings are done in "design_basic_settings.cmd". |
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obsolete |
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obsolate |
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program_fpga_bitfile.cmd | available | (optional) Programming FPGA via JTAG with specified "<design_name>.bit". Used LabTools Programmer (Vivado or LabTools only), depends on |
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installation settings. Default, it used |
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the "<design_name>.bit" from: |
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"<project folder>/prebuilt/hardware/<board_file_shortname>". Settings are done in "design_basic_settings.cmd". | ||
labtools_open_project_guimode.cmd | available | (optional) |
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Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd". |
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Intenal Development | ||
development_design_run_prebuilt_all_batchmode.cmd | internal available | (only Trenz Internal) Create files for all variants |
development_utilities_backup.cmd | internal available | (only Trenz Internal) Create ZIP file |
development_xsct_console.cmd | internal available | (only Trenz Internal) Start XSCT Console on Vitis workspace |
File Name | Status | Description |
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Design + Settings | ||
_create_linux_setup.sh | available | Use to create bash files. With 2018.3 and newer also "Module Selection Guide" is included and with 2022.2 prebuilt export for the selected variant |
design_basic_settings.sh | available | Settings for the other *.cmd files. Following Settings are avaliable:
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design_clear_design_folders.sh | not available | (optional) |
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Attention: Delete " |
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<project folder>/v_log/", " |
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<project folder>/vivado/", " |
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<project folder>/vivado_lab/", " |
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<project folder>/sdsoc/", and " |
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<project folder>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files |
design_run_project_bashmode.sh |
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available | (optional) |
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Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. |
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Delete "<project folder>/vivado/", and " |
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<project folder>/workspace/ |
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sdk/" directory with related documents before Project will created. | ||
Hardware Design | ||
vivado_create_project_guimode.sh | available | Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete " |
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<project folder>/vivado/", and " |
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<project folder>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. | ||
vivado_create_project_bashmode.sh | not available | (optional) |
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Create Project with setting from "design_basic_settings.cmd" and source folders. |
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Delete "<project folder>/vivado/", and " |
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<project folder>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. | ||
vivado_open_existing_project_guimode.sh | available | Opens an existing Project " |
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<project folder>/vivado/<design_name>.xpr" and restore Script-Variables. | ||
Software Design | ||
sdk_create_prebuilt_project_guimode.sh | not available | (optional) Create SDK project with hardware definition file from prebuild folder. It used the *. |
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hdfxsa from: |
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"<project folder>/prebuilt/hardware/<board_file_shortname>/". Set "<board_file_shortname> |
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" and "<app_name>" in "design_basic_settings.cmd". | ||
Programming | ||
program_flash |
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.sh | not available | (optional) |
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Programming Flash Memory via JTAG with specified |
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*.bin |
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(Zynq devices) or *.mcs (native FPGA). Used LabTools Programmer (Vivado or LabTools only |
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. Default, it used the boot.bin from: |
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"<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>". Settings are done in "design_basic_settings. |
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sh". |
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labtools_open_ |
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project_ |
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guimode.sh | not available | (optional) |
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(optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".
Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd". | ||
Intenal Development | ||
development_design_run_prebuilt_all_batchmode.sh | internal available | (only Trenz Internal) Create files for all variants |
development_utilities_backup.sh | internal available | (only Trenz Internal) Create ZIP file |
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Name | Options | Description (Default Configuration) |
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TE::help | Display currently available functions. Important: Use only displayed functions and no functions from sub-namespaces | |
Hardware Design | ||
TE::hw_blockdesign_create_bd | [-bd_name] [-msys_local_mem] [-msys_ecc] [-msys_cache] [-msys_debug_module] [-msys_axi_periph] [-msys_axi_intc] [-msys_clk] [-help] | Create new Block-Design with initial Setting for PS, for predefined bd_names: |
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Type TE::hw_blockdesign_create_bd -help for more information | ||
TE::hw_blockdesign_export_tcl | [-no_mig_contents] [-no_validate] [-mod_tcl] [-svntxt <arg>] [-board_part_only] [-help] | Export Block Design to project folder |
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"<project folder>/block_design/" . Old *bd.tcl will be overwritten! | ||
TE::hw_build_design | \[-disable_synth\] \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\] | Run |
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synthesis, Implement, and generate Bit-file, optional MCS-file and some report files | ||
Software Design | ||
| [-run_only] [-prebuilt_hdf <arg>] [-no_hsi] [-no_bif] [-no_bin] [-no_bitmcs] [-clear] [-help] | obsolete Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set. |
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Definition file to the working directory: |
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"<project folder>/workspace/hsi" |
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in "<project folder>/workspace/hsi" for all |
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Programs listed in |
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"<project_ |
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folder>/sw_lib/apps_list.csv" |
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prebuilt folders "<project folder>/prebuilt/..."
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[-open_only] [-update_hdf_only] [-prebuilt_hdf <arg>] [-clear] [-help] | obsolete Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set. |
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Definition file to the working directory: |
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"<project folder>/workspace/sdk" |
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TE:: |
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sw_ |
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run_ |
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vitis | [- |
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all] [-gui_only] [-no_gui] [-workspace_only] [-prebuilt_xsa_only] [-prebuilt_xsa <arg>] [-clear] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, |
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if - |
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prebuild_ |
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xsa <arg> or -prebuilt_xsa_only isn't |
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(MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
selected. Copy the XSA File to the working directory: "<project folder>/workspace/sdk" Generates Vitis workspace with platform project and start Vitis. Optional parameter
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TE::sw_run_plx | [-run] [-config] [-u-boot] [-kernel] [-rootfs] [-bootscr_opt <arg1> <arg2> <arg3> <arg4>] [-devicetree <arg>] [-app <arg>] [-disable_clear] [-clear |
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] [-help] | Attention: |
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Beta usage only for Linux OS
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Programming | ||
TE::pr_init_hardware_manager | [-help] | Open Hardware manager, autoconnect target device and initialise flash memory with configuration from *_board_files.csv. |
TE::pr_program_jtag_bitfile | [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_bitfile] [-help] | If "-used_basefolder_ |
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bitfile" is set, the |
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Bitfile (*. |
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bit) |
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from the base folder ( |
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"<project folder>") is used instead |
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of the |
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prebuilds. Attention: Take only one |
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Bitfile in the basefolder! (MicroBlaze only) If "-swapp" is set, the |
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Bitfile with *.elf configuration is used from |
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"<project_ |
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folder>/prebuilt/boot_images/<board_file_shortname>/<app_name> |
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" |
TE:: |
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pr_ |
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program_ |
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flash | [- |
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swapp <arg>] [-swapp_av] [- |
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reboot] [- |
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erase] [- |
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Make a Backup from your Project in <design_name>/backup/
Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported.
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Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state.
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setup] [-used_board] [-basefolder] [-def_fsbl] [-help] | Program flash with the given swapp from the prebuilt folder ("<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"). | |
TE::pr_putty | [-available_com] [-com] [-speed] [-help] | Show available COM ports and open automatically the UART COM port, in case only one is selectable Important:
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Utilities | ||
TE::util_zip_project | [-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help] | Make a Backup from your Project in "<project folder>/backup/" Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported. |
TE::util_editor | [-file <arg>] [-help] | open file with editor which is set on "TE_EDITOR" Enviroment variable |
TE::util_terminal | [-help] | linux only. open new terminal |
TE::util_package_length | [-help] | Export Package IO length information to *.csv on the doc folder |
TE::util_svn | [-status] [-update] [-add <arg>] [-remove <arg>] [-commit <arg>] [-commit\] [-help] | start svn commands on the current project(project must be under SVN Version) On Win OS: Need Tortouise SVN with command line tools installation On Linux: Need subversion installed, for example sudo apt-get install subversion -y |
Beta Test (Advanced usage only!) | ||
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TE::ADV::beta_hw_remove_board_part | [-permanent] [-help] | Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported. |
TE::ADV::beta_hw_export_rtl_ip | \[-help\] | Save IPs used on rtl designs as *.xci in "<project folder>hdl/xci". If sub folder "<board_file_shortname>" is defined this will be saved there. |
TE::ADV::beta_hw_create_board_part | \[-series <arg>\] \[-all\] \[-preset\] \[-existing_ps\] \[-help\] | create PS or preset.xml PS settings from external tcl scripts |
TE::ADV::beta_hw_export_binary | \[-mode <arg>\] \[-app <arg>\] \[-folder <arg>\] \[-all\] \[-help\] | export prebuilt files to an given folder (based from project folder). Special folder is used, if empty |
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Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin) or FPGA-Device Flash Programming (*.mcs):
Run “program_flash.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash -swap <app_name>” on Vivado TCL-Console
Used .bin(Zynq)/.mcs(native FPGA) "<project folder>/prebuilt/boot_images/<board_file_shortname>/<app_name>"
13. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from "<project folder>
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/prebuilt/boot_images/<board_file_shortname>/<app_name>
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"
Files | Note |
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<project folder>/design_basic_settings.cmd/sh | General local variables for project generation |
<project folder>/settings/design_settings.tcl | Design setting like Device Filter, UART Speed and Port |
<project folder>/settings/development_setting.tcl | Development settings which can manipulate execution steps |
Name | Value | Note |
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TE_SERIAL_PS | <path> | Internal usage only |
TE_COM | <path> | path to putty, in case it's not installed global |
TE_TIMEOUT | <time> | timeout for jobs, unit in minutes, def 120 |
TE_RUNNING_JOBS | <count> | max jobs (depends on available CPUs) which can be started by Vivado, default 4 |
TE_WSL_USAGE | 1/0 | 1 use Windows programs for some external processes |
TE_GUI_DISABLED | 1/0 |
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TE_EDITOR | <name> | Text Editor which should be started for some TE functions |
TE_PLX_SSTATE_CACHE_DOWNLOAD | <path> | Local version of SSTATE, file avialable on the download area from Xilinx petalinux, example: TE_PLX_SSTATE_CACHE_DOWNLOAD="~/design/sstate-cache/downloads_2023.2/downloads" |
PLX_SSTATE_CACHE_AARCH64 | <path> | Local version of SSTATE for U+ Zynq and Versal, file avialable on the download area from Xilinx petalinux, example: TE_PLX_SSTATE_CACHE_DOWNLOAD="~/design/sstate-cache/downloads_2023.2/downloads" |
PLX_SSTATE_CACHE_ARM | <path> | Local version of SSTATE for Zynq 7000, file avialable on the download area from Xilinx petalinux, example: PLX_SSTATE_CACHE_ARM="~/design/sstate-cache/sstate_arm_2023.2/arm" |
PLX_SSTATE_CACHE_MB_FULL | <path> | Local version of SSTATE for Microblaze, file avialable on the download area from Xilinx petalinux, example: PLX_SSTATE_CACHE_ARM="~/design/sstate-cache/sstate_mb_full_2023.2/mb_full" |
PLX_SSTATE_CACHE_MB_LITE | <path> | currently not supported |
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Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin):
Run “program_flash_binfile.cmd”
9. (optional) FPGA-Device Flash Programming (*.mcs):
Run “program_flash_mcsfile.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
13. (optional) FPGA-Device Flash Programming (*.mcs):
Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
14. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
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More details see TE Board Part Files
Board Parts are located on subfolder "board_files", with the name of the special board. Revisions are
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split in the subfolder of the board part <boardpart_name><version>
Every Version of a Board Parts consists of four files:
Board Part Extensions are TCL-Scripts, which can be sourced in Vivado Block Design. Thy are usable with TE-Scripts only. It contains additional settings of PS-settings or special carrier-board design changes.
Use Reference Designs or Vivado TCL-Console (TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation"
Possible:
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Board Part csv file is used for TE-Scripts only.
Name | Description | Value |
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ID | ID to identify the board variant of the module series, used |
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in TE-Scripts | Number, should be unique in csv list | |
PRODID | Product ID | Product Name |
PARTNAME | FPGA Part Name, used in Vivado and TE-Scripts | Part Name, which is available in Vivado, ex. xc7z045ffg900-2 |
BOARDNAME | Board Part Name, used in Vivado and TE-Scripts |
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"<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32
Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build.
For Zynq and ZynqMO only Flash name is necessary
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set Board Part Name or "NA", which is available in Vivado, NA is not defined to run without board part and board part ex. trenz.biz:te0782-02-45:part0:1.0 | ||
SHORTNAME | Subdirectory name, used for multi board projects to get correct sources and save prebuilt data | name to save prebuilt files or search for sources |
ZYNQFLASHTYP | Flash type used for programming Zynq-Devices via SDK-Programming Tools (program_flash) | "qspi_single" or "NA", NA is not defined |
FPGAFLASHTYP | Flash type used for programming Devices via Vivado/LabTools | "<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32 Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build. For Zynq and ZynqMO only Flash name is necessary |
PCB_REV | Supported PCB Revision | "<supported PCB Revision>|<supported PCB Revision>", for ex. "REV02" or "REV03|REV02" |
DDR_SIZE | Size of Module DDR | use GB or MB, for ex. "2GB" or "512MB" or "NA" if not available |
FLASH_SIZE | Size of Module Flash | use MB, for ex. "64MB" or "NA" if not available |
EMMC_SIZE | Size of Module EMMC | use GB or MB, for ex. "4GB" or "NA" if not available |
OTHERS | Other module relevant changes to distinguish assembly variants | |
NOTES | Additional Notes | |
DESIGN | Specify the allowed variants for different designs. | see also <design folder>\settings\design_settings.tcl |
CONFIG_SW_EXTPLL | Optional parameter to support different PLL Versions which can be programmed Replace all files with the same file name on sw_lib folder with the specified one | relativ path to the source file, for example "./misc/PLL/SI5345_D/te_Si5345-Registers.h" |
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Recommended BD-Names (currently importend for some TE-Scripts):
Name | Description |
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zsys |
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Identify project as Zynq Project with processor system (longer name with *zsys* are supported too) |
zusys |
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Identify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too) |
msys |
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Identify project as Microblaze Project with processor system (longer name with *msys* are supported too) |
fsys |
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Identify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too) |
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Recommended XDC-Names (used for Vivado XDC-options):
Property | Name part | Description |
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Set Processing Order | *_e_* | set to early |
*_l_* | set to late | |
set to normal | ||
Set Used In | *_s_* | used in |
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synthesis only | |
*_i_* | used in implement only |
used in both, |
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synthesis and implement |
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Attention not all features of the TE-Scripts are supported in the advanced usage!
To
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modify current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.
See Chapter Board Part Files for more information.
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TCL Files from "
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<project folder>/settings/usr" will be load
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automatically on script initialisation.
SDSOC description and files to generate SDSoC project are deposited on the following folder: "
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<project folder>/settings/sdsoc"
HDL files can be saved in the subfolder "
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<project folder>/hdl/" as single files or
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<project folder>/hdl/folder/ and all subfolders or "
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<project folder>/hdl/<shortname>" and all subfolders of "
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<project folder>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.
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A own top-file must be specified with the name "
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<project folder>_
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top.v" or "
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<project folder>_top.vhd".
To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for
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synthesis only.
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IP-cores (*.xci). can be saved in the subfolder "
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<project folder>/hdl/xci" or "
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<project folder>/hdl/xci/<shortname>". They will be loaded automatically on project creation.
IP -TCL
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description (*_preset.tcl). can be saved in the subfolder "
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<project folder>/hdl/tcl" or "
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<project folder>/hdl/tcl/<shortname>". They will be loaded automatically on project creation.
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To get content of older
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revision got to "Change History"
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of this page and select older revision number.
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Date | Revision | Vivado Version | Authors | Description | ||||||||||||||||||||||
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| 2022.2 |
| working in process | ||||||||||||||||||||||
2023-08-15 | v.176 | 2022.2 | John Hartfiel | Last Vivado 2022.2 supported project delivery version | ||||||||||||||||||||||
2023-02-06 | v.171 | 2021.2 | John Hartfiel | Last Vivado 2021.2 supported project delivery version | ||||||||||||||||||||||
2021-05-06 | v.162 | 2020.2 | Manuela Strücker | Last Vivado 2020.2 supported project delivery version | ||||||||||||||||||||||
2020-11-26 | v.157 | 2019.2 | John Hartfiel | Last Vivado 2019.2 supported project delivery version | ||||||||||||||||||||||
2019-12-18 | v.148 | 2018.2 | John Hartfiel | Last Vivado 2018.3 supported project delivery version |
--- | --- | 2018.2 | John Hartfiel | Last Vivado 2018.2 supported project delivery version
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2019-07-10 |
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v.142 | 2017.4 | John Hartfiel | Last Vivado 2017.4 supported project delivery version | |
2017-11-03 | v.134 | 2017.2 | John Hartfiel | Last Vivado 2017.2 supported project delivery version |
2017-09-12 | v.131 | 2017.1 | John Hartfiel | Last Vivado 2017.1 supported project delivery version |
2017-04-12 | v.126 | 2016.4 | John Hartfiel | Last Vivado 2016.4 supported project delivery version |
2017-01-16 | v.114 | 2016.2 | John Hartfiel | Last Vivado 2016.2 supported project delivery version |
2016-06-21 | v.83 | 2015.4 | John Hartfiel | Last Vivado 2015.4 supported project delivery version |
2013-03-11 | v.1 | --- | Antti Lukats | Initial release |
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