24 MHz Clock Oscillator
The module has a 24 MHz SMD clock oscillator providing a clock source for both the EZ-USB FX2LP USB FX2 microcontroller (XTALIN) and the FPGA as detailed in the table below.
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| title | 24 MHz clock signal details. |
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24MHZ1 | IO_L28N_2
GCLK3 | AE14 | 2 |
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Digital Clock Manager (DCM)
The DCMs of the FPGA can be used to synthesize arbitrary clock frequencies from any on-board clock network, differential clock input pair or single-ended clock input. For further reference, please read Xilinx DS485:Digital Clock Manager (DCM) Module and the DCM chapter in Xilinx UG331: Spartan-3 Generation FPGA User Guide.
Interface Clock (IFCLK)
The IFCLK line synchronizes the communication between the EZ-USB FX2LP USB FX2 microcontroller and the FPGA as detailed in the table below.
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| title | Interface clock (IFCLK) signal details. |
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IFCLK | IO_L31N_1
TRDY1
RHCLK3 | P25 | 1 |
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Main Clock Oscillator
The module has a main SMD clock oscillator providing a clock source for the FPGA as detailed in the table below.
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| title | Main clock signal details. |
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| | | | MAINCLK | IO_L27N_2
GCLK1 | AA14 | 2 |
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Standard frequency is 100 MHz. Should you wish or need another main clock oscillator frequency, please contact Trenz Electronic. The lower the main clock frequency, the lower the module power consumption. Moreover, as the main clock is preferably used as DDR SDRAM clock, a lower clock frequency makes easier for the development tools to meet the timing requirements (particularly for DDR SDRAM).
Watchdog Timer
TE0320 has a watchdog timer that is periodically triggered by a positive or negative transition of the watchdog input (WDI) signal. When the supervising system fails to retrigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the watchdog output becomes active and asserts the master reset (/MR) signal. This event also reinitializes the watchdog timer.
If resistors R135 and R165 R136 are not populated, the watchdog is disabled.
If resistors R135 and R165 R136 are populated, the watchdog can be enabled . In this case there are still two options.(or not).
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| R135 (bottom side). | R136 (top side). |
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Any other combination of resistors R135 and R136 is not supported. |
If resistors R135 and R136 are populated, there is two configuration possible.
- To enable the watchdog after module power-up, drive the WDI signal to generate a transition (no matter if positive or negative).
- To keep the watchdog disabled, set the WDI FPGA signal output to high-impedance. One way to reach this goal is to leave FPGA pin V24 (FPGA signal IO_L19P_1) undeclared in the user constraints file (UCF) and set the Xilinx Project Navigator options as follows: project properties > configuration options > unused IOB pins > float.
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| title | Configuration option in Xilinx ISE Project Navigator. |
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Image Removed | Image Removed |
R135 (bottom side). | R136 (top side). |
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| Any other combination of resistors R135 and R136 is not supported. |