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Table of Contents |
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The Trenz Electronic TEI0016 is an a commercial-grade module based on Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0016-info for the current online version of this manual and other available documentation.
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Intel® MAX 10 Commercial [10M08SAU169C8G]
SDRAM Memory up to
64Mb, 166MHz 32 Mbyte (8Mbyte default)
USB 2.0
Dual High Speed USB to Multipurpose UART/FIFO IC
- Quad SPI Flash, 64Mb
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)
EEPROM Memory, 4Kb- 8x User LED
Micro USB
portConnector
18 16 Bit Analog to Digital Converter with 1 MSPS or 500 kSPS
2x SMA Female Connector
I/O interface: 23x GPIO
Power Supply: 5V (from USB)
Dimension: 25 mm x 86.5 mm
Others:
Others:
Dimension: 86m x 25m
Block Diagram
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add drawIO object here.
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| title | TEI0016 block diagram |
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| revision | 413 |
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| diagramName | TEI0016_OV_BD |
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| simpleViewer | false |
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| title | TEI0016 main components |
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| revision | 15 |
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| diagramName | TEI0016_OV_MC |
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| simpleViewer | false |
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| links | auto |
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| tbstylediagramWidth | 639hidden |
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 Image Modified
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- SMA Connector, J5...6
- Instrumentation Amplifier, U12
- Analog to Digital ConvertorConverter, U6
- Voltage Reference, U8
- Voltage Regulator, U10 - U13 - U16
- Buck Switching Voltage Regulator/LDO, U11 - U4
- SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1
- SPI Flash Memory, U5 (not populated)
- 12.00 MHz MEMS oscillatorOscillator 12MHz, U7
- FTDI USB to JTAG/UART convertor/FIFO, U3
- User LEDs, D2...9
- 4Kb EEPROM, U9
- Configuration LED (Red) , D10
- Power-on LED (Green), D1
- SwitchPush button, S1...2
- Micro USB portConnector, J9
- 1x14 pin header, J2 (Not assembled)
- 1x6 pin header, J4 Pin Holder (Not assembled)
- Jumper, J3
- 1x14 pin header, J1 (Not assembled) J1...4
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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Quad SPI Flash | N/A | Not Programmedpopulated | | EEPROM | Programmed | FTDI configuration | SDRAM | Not Programmed |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.
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| anchor | Table_OV_RST |
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| title | Reset process. |
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Signal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | connected Connected to nCONFIG |
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Signals, Interfaces and Pins
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| anchor | Table_OBP_IOs |
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| title | FPGA I/O Banks |
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| FPGA Bank | I/O Signal Count | Connected to | Notes |
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| Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | | 1 | Jumper, J3 | AIN7 | | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 | | 5 |
A2D| ADC, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | | 1 | 12MHz Oscillator, U7 | CLK12M | | 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | | 2 | 1x14 Pin header, J1 | DIO0...1 | | 1 | D12_R | DIO12 | | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | | 2 | SDRAM, U2 | DQM0...1 | | 1 | D11_R | DIO11 | Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 | | 6 | SPI Flash, U5 | F_CS, F_ |
CK| CLK, F_DI, F_DO, nSTATUS, DEVCLRn | | 1 | Red LED, D10 | CONF_DONE | | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | | 1 | Push Button, S2 | USER_BTN |
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JTAG Interface
Micro-USB Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PCJTAG access to the TEI0015 SoM through pin header connector J4.
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| anchor | Table_SIPOBP_JTGUSB |
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| title | JTAG Micro USB-2 connector pins connection |
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| orientation | portrait |
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| sortDirection | ASC |
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JTAG Signal | Pin Header ConnectorTMS | J4-6 | TDI | J4-5 | TDO | J4-4 | TCK | J4-3 | JTAG_EN | J4-2 | |
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| anchor | Table_OBP |
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| title | On board peripherals |
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SDRAM
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| anchor | Table_OBP_SDRAM |
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| title | SDRAM interface IOs and pins |
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Signal Schematic Name
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A0 ... A13
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BA0 / BA1
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bank 3
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DQ0 ... DQ15
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bank 6
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DQM0 ... DQM1
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bank 6
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CS
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bank 3
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CKE
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bank 3
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RAS
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bank 3
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Row Address Strobe
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CAS
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bank 3
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Column Address Strobe
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FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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FPGA bank 1B, pin G1
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| VBUS | USB_VBUS |
| | D+ | FTDI U3, DP pin |
| | D- | FTDI U3, DM pin |
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JTAG Interface
JTAG access to the TEI0016 SoM through pin header connector J4.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| cellHighlighting | true |
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JTAG Signal | Pin Header Connector | Note |
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| TMS | J4-6 |
| | TDI | J4-5 |
| | TDO | J4-4 |
| | TCK | J4-3 |
| | JTAG_EN | J4-2 | Pulled-up to 3.3V. |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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SDRAM
TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_SDRAM |
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| title | SDRAM interface IOs and pins |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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| Address inputs | A0 ... A13 | bank 3 | - | Bank address inputs
| BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 | - | | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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FTDI FT2232H
The FTDI chip U3 converts signals from USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface | | ADBUS1 | TDI | FPGA bank 1B, pin F5 | | ADBUS2 | TDO | FPGA bank 1B, pin F6 | | ADBUS3 | TMS | FPGA bank 1B, pin G1 | | BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | User configurable | | BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | User configurable | | BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | User configurable | | BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | User configurable | | BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | User configurable | | BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | User configurable | | BDBUS6 | BDBUS6 | FPGA bank 6, pin C11 |
| | BDBUS7 | BDBUS7 | FPGA bank 3, pin J7 |
| | BCBUS0 | BCBUS0 | FPGA bank 5, pin J9 |
| | BCBUS1 | BCBUS1 | FPGA bank 3, pin K5 |
| | BCBUS2 | BCBUS2 | FPGA bank 3, pin K5 |
| | BCBUS3 | BCBUS3 | FPGA bank 3, pin K5 |
| | BCBUS4 | BCBUS4 | FPGA bank 3, pin K5 |
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SPI Flash
Optional SPI flash device maybe assembled in custom variants, normally it is not populated
SPI Flash Memory
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
| Scroll Title |
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| anchor | Table_OBP_QSPI |
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| title | Quad SPI Flash memory interface |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Signal Schematic Name | Connected to | Notes |
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| F_CS | FPGA bank 8, pin B3 | chip Chip select | | F_CLK | FPGA bank 8, pin A3 | clockClock | | F_DI | FPGA bank 8, pin A2 | data Data in / out | | nSTATUS | FPGA bank 8, pin C4 | data Data in / out, configuration dual-purpose pin of FPGA | | DEVCLRN | FPGA bank 8, pin B9 | data Data in / out, configuration dual-purpose pin of FPGA | | F_DO | FPGA bank 8, pin B2 | data Data in / out |
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EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Connected to | Notes |
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EECS | FTDI U3, Pin EECS |
| | EECLK | FTDI U3, Pin EECLK |
| | EEDATA | FTDI U3, Pin EEDATA |
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A2D Convertor
The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).
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| anchor | Table_OBP_A2D |
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| title | A2D converter interface and pins |
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IN+
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ADC
The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS,
boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 1MSPS.
The ADC can be distinguished via its part code:
- TEI0016-03-08-C8A: ADAQ7988BCCZ - 16-bit 500kSPS - starts with Y6H
- TEI0016-03-08-C8B: ADAQ7980BCCZ - 16-bit 1.0MSPS - starts with Y6F
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| anchor | Figure_OV_BD |
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| title | TEI0016 part code variants |
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| border | true |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramName | TEI0016_part-code-variants |
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| simpleViewer | false |
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| width | 600 |
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| diagramWidth | 1922 |
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| revision | 1 |
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| Scroll Title |
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| anchor | Table_OBP_LEDADC |
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| title | On-board LEDsADC converter interface and pins |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Designator| Color | Active LevelNote | | D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on | |
Micro-USB2 Connector
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IN+ | U8, VOUT |
| | IN- | U12, VOUT |
| | SDI | Bank 2, ADC_SDI |
| | SDO | Bank 2, ADC_SDO |
| | SCK | Bank 2, ADC_SCK |
| | CNV | Bank 2, ADC_CNV |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_USBLED |
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| title | Micro USB-2 connector pinsOn-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Pins | Connected to | Active Level | Note |
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| VBUS | USB_VBUS | It is connected to GND | D+ | FTDI U3, DP pin | D- | FTDI U3, DM pin | |
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| D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on. |
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Push Buttons
| Scroll Title |
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| anchor | Table_OBP_CLKLED |
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| title | OsillatorsOn-board Push Buttons |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Source | Schematic Name | Frequency | Note |
|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
Power and Power-On Sequence
...
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| Designator | Connected to | Functionality | Note |
|---|
| S1 | RESET | General reset |
| | S2 | USER_BTN | User push button | Connected to FPGA Bank 8. |
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Clock Sources
Power Supply
To power-up the module, power supply with minimum current capability of 1A is recommended.
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| Scroll Title |
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| anchor | Table_PWROBP_PCCLK |
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| title | Power ConsumptionOsillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| Power Input Pin | Typical Current |
|---|
| VIN | TBD* |
* TBD - To Be Determined
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| Clock Source | Schematic Name | Frequency | Note |
|---|
| MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3. Connected to FPGA bank 2, pin H6. |
|
Power and Power-On Sequence
| Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
The module is supplied from USB (optionally via unpopulated pin header).
Power Consumption
| Scroll Title |
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| anchor | FigureTable_PWR_PDPC |
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| title | Power DistributionConsumption |
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| ignoredrawioborderfalseviewerToolbartruefitWindowfalsediagramDisplayNamelbox | true |
| revision | 3 |
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| diagramName | TEI0015_PWR_PD |
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| simpleViewer | false |
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width | | links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Removed
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| 1 | | sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | Typical Current |
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| Intel MAX 10 10M08 FPGA | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
| Scroll Title |
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| anchor | Figure_PWR_PSPD |
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| title | Power SequencyDistribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 34 |
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| diagramName | TEI0015TEI0016_PWR_PSPD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641545 |
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Voltage Monitor Circuit
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
 Image Added
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Power-On Sequence
There is no specific or special power-on sequence, just one single power source is needed. After power on, the green LED (D1) will be on.
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Designator| VCC / VCCIO Schematic Name | VoltageJ2 Pin | Connector J9 Pin | Direction | Notes |
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| VIN | J2-13 |
VIN5V | Input| Input | 5 V - Pin Header | | 3.3V |
3.3V5VJ9 | 5V| J9-1 | Input | 5 V - USB Connector |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq Intel Max 10 SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| Bank 1A | VCCIO1A | 3.3V | Bank 1B | VCCIO1B | 3.3V | Bank 2 | VCCIO2 | 3.3V | Bank 3 | VCCIO3 | 3.3V | Bank 5 | VCCIO5 | 3.3V | Bank 6 | VCCIO6 | 3.3V | Bank 8 | VCCIO8 | 3.3V |
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use "include page" macro and link to the general B2B connector page of the module series,
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
| VCCIO1A | 3.3V |
| | Bank 1B | VCCIO1B | 3.3V |
| | Bank 2 | VCCIO2 | 3.3V |
| | Bank 3 | VCCIO3 | 3.3V |
| | Bank 5 | VCCIO5 | 3.3V |
| | Bank 6 | VCCIO6 | 3.3V |
| | Bank 8 | VCCIO8 | 3.3V |
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Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute Absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit | Reference Document |
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VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | | I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | | Voltage on ADC IC U15 pins | -5.0 | 5.0 | V | AD4003BCPZ datasheet | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | VIN | Supply voltage | 4.75 | 5.25 | V |
| | CH1-, CH1+ | Analog input voltage on amplifier U12 pin 1, 10 | -30 | 30 | V | AD8251 datasheet | T_STG |
AD4003BCPZ datasheet | Storage Temperature | -40 | +85 | °C |
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Recommended Operating Conditions
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Min | Max | Unit | Reference Document |
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| VIN supply |
voltage (5.0V nominal)4.75 | 5.25 | V | | I/O Input voltage for FPGA I/O bank | -0.5 | 4.12 | V | Intel MAX 10 datasheet | | Voltage on ADC IC U15 pins | -0.1 | 5.1 | V | AD4003BCPZ datasheet | | Analog reference voltage on IC U15 | 5.0 | 5.0 | V | AD4003BCPZ datasheet | Storage Temperature | | voltage (5.0V nominal) | 4.75 | 5.25 | V |
| | Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+) | -10 | 10 | V |
| | T_OP | 0 | +70 | °C | W9864G6JT-6 datasheet |
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Physical Dimensions
Module size:
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86.5 mm ×
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25 mm. Please download the assembly diagram for exact
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numbers.
PCB thickness: ?? 1.22 mm.
| Page properties |
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 12 |
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| diagramName | TEI0015TEI0016_TSTE_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Removed Image Added
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Currently Offered Variants
| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Revision History
Hardware Revision History
| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
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| 2019-02-11 | 01 | - | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
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| anchor | TableFigure_VCPRV_SOHRN |
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| title | Trenz Electronic Shop Overview Board hardware revision number. |
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tablelayout |
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Trenz shop TE0728 overview page |
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| English page | German page |
Revision History
Hardware Revision History
List of online PCN ...Link
| ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 1 |
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| diagramName | TEI0016_RV_HRN |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 154 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Added
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| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes |
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Document Change History
| Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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change list | - major cleanup multiply sections
| | v.56 | Kilian Jahn | - update notes for variants
| | 2019-06-05 | v.55 | ED | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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