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The reference architecture can be tested in two ways:
Two types of connections are available:
Xilinx EDK/SDK and iMPACT (or equivalent XMD console commands) could be used to develop/generate an FPGA bitstream (with MicroBlaze's processor and software "merged" into an FPGA bitstream). When the FPGA bitstream is ready, either the USB or JTAG connection could be used to write the SPI Flash memory of the TE USB FX2 module (i.e. download the FPGA bitstream into the SPI Flash memory).
The JTAG connection could also be used to directly download the FPGA bitstream into the FPGA without the need of a reset.
The JTAG connection could be used with Xilinx EDK and SDK GUIs for development and debug purposes; XMD console could also be used.
The USB connection CANNOT be used with Xilinx EDK and SDK GUIs for development and debug purposes. The USB connection should be used after the development and debug process.
With a JTAG connection, the development and debug phases are easier.
Without a JTAG connection, the user/developer should create/use custom functions/programs for the debug phase but some JTAG debug features may not be easily replicated through a USB connection.
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Use of JTAG connection is NOT necessary. |
To test the USB communication in the Reference Architecture case is necessary:
For an example see here.
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Use of JTAG connection is necessary. |
To completely test the Reference Architecture is necessary:
The procedures are the following (a TE0300 board case is described).
.bit or .mcs direct download iMPACT, OpenFut or OpenFutNet | Procedure SDK: opening and update SDK project only Compile and link time less than 1 minute. | Procedure XPS+SDK: opening and update both XPS and SDK projects Resynthesis of reference HW could take from 10 minutes to 1 hour(1) |
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Skip. | Skip. | Update XPS project from an old version to a new one |
Skip. | Skip. | |
Skip. | Open SDK project and (if needed) update the SDK project from an old version to a new one | Recreate SDK project using the new exported HW project |
Skip. | Generate a new link script | |
Download the reference bitstream to the FPGA using iMPACT, Open_FUT or OpenFutNet | Download the reference bitstream to the FPGA using SDK | |
Skip. | Run the demo project to run on board tests | |
Check the fiirmware of FX2 microcontroler | ||
USB communication tests + DMA tests |
(1) It depends on which computer is used (workstation, regular PC or low-end PC).
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For old version of Xilinx EDK with older version of Project Reference (they do no longer exist on GitHub) the procedure is the folowing
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To To use the "demo" application contained in TE0xxx-Reference-Designs\reference-TE0xxx\SDK\SDK_Workspace, you should : (1) copy GitHub's "TE-EDK-IP" folder (from https://github.com/Trenz-Electronic/TE-EDK-IP) to the folder that contains the folder "reference-TE0xxx":
otherwise you must copy the contents of GitHub's 'TE-EDK-IP' folder inside the already existent empty folder "TE0xxx-Reference-Designs\TE-EDK-IP".
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From now on, the choice (a) is assumed. |
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You should not alter folder nesting (double nesting) because is a Xilinx Platform Studio requirements |
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From now on, the choice (1) is assumed. |
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The FX2 microcontroller on the TE USB FX2 module
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You should not alter folder nesting or select MyProcessorIPLib because double nesting of folders is a Xilinx Platform Studio requirements |
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The HW implementation usually takes some time; if you have a very slow computer, the new synthesis could require an hour. |
When Xilinx SDK open, you should:
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should contain valid firmware before proceeding.
If the HDL design was successfully implemented and downloaded to the TE0300/TE0320/TE0630 family module, you can proceed to compile the MB software. Press the "build all user applications" button.
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Demo program (running on MicroBlaze) will work even in case the UART port is left unconnected: it is not necessary to use a USB/Uart converter or Uart port on a PC, if you are using XMD UART HDL block. |
PLACEHOLDER START
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The UART settings are:
bits per seconds: 115,200
data bits: 8
parity: none
stop bits: 1
flow control: none (otherwise you will not be able to enter commands)
The UART port will output something of tis kind:
-Entering main TE0300 DEMO ver 0x07010218-
Setting up Interrupt Controller:
Initialize exception handling
Register external interrupt handler
Register I2C_SLAVE interrupt handler
Enable interrupts in the interrupt controller
Start the interrupt controller
Enabling and initializing instruction cache
Enabling and initializing data cache
Type:
'a' RAM test
'f' RAM Ftest
'c' toggles caching
'g' prints switches state and board revision
't' starts TX transmission
'r' starts RX transmission
's' stops all transmissions
'm' for the redraw menu
MicroBlaze will work even in case the UART port is left unconnected.
PLACEHOLDER STOP
To use the demo project without the XMD UART, you need to use "RS232" instead of "debug_module" as standard in/out port. Otherwise the application running on the Microblaze processor freezes if you disconnect the XMD. To accomplish that you need to set up the Microblaze "Software Platform Settings".
The UART is then redirected to external pins, which are defined in the data/system.ucf file. The following snippet shows the case of the TE0300 series modules:
Module RS232 constraints*
Net fpga_0_RS232_RX_pin LOC=B13;
Net fpga_0_RS232_TX_pin LOC=B14;
Please refer to Table 1 for other module series relevant to this application note.
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