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Template Revision 1.1

For carrier - module combination, create main getting started page for carrier Design Name always "TE Series Name" +Getting Started, for example "TE0701 Getting started" and add carrier/module combination in the description → link on the module resource page also

For whole board,  use the board name, for example "TEBF0911 Getting Started"

  • Change List 1.0 to 1.1
    • add table of content to sidebar


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In this section you must explain how to power on the board and run the Reference Design (test board) on the particular module. The main points must be mentioned are:

  • Overview of the board (point out the LEDs, Ethernets, Switches and etc on the board overview)
  • Explain Switches functionality
  • Explain user LEDs

  • Explain the UART connection

  • Refer to the Reference Design

    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Overview

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Power supply

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The input power supply must be mentioned.

Over Micro USB or VIN Pin (5V) possible.

JTAG/UART

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Explain JTAG or UART connection breifly.

JTAG and UART connections are available through Micro USB connector.  External JTAG Programmer is not needed.

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Pin name

Connected to

DirectionNote
BDBUS0E18inuart rx
BDBUS1F16outuart tx


Push Buttons

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Explain all DIP switches functionality.

  • Reset Button: reset Cyclone V (connected to nCONFIG Pin)
  • User Button: connected to FPGA Pin L17

LEDs

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Explain all user LEDs functionality and connections.

There are 2 status LEDs and 8 user LEDs and which can be used for variant purposes.


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NameColorConnected toActive LevelNote
Power LEDGreen3.3Vlow3.3V status LED
CONF_DONERedCONF_DONE pinhigh--
LED1RedP4high--
LED2RedM4high--
LED3RedM3high--
LED4RedN3high--
LED5RedV2high--
LED6RedL2T2high--
LED7RedL1high--
LED8RedK1high--


CRUVI Pin Header J3

The Pin Header J3 is based on CRUVI Standard. For more information, please visit www.cruvi.com.

The Pins of the pin header J3 are connected to the FPGA Bank 7A and 8A. With the VSEL pin (connected to N10) the voltage of these banks (VADJ) must be selected between 1.8V and 3.3V (depends on connected periphery):

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VSEL

VADJ voltage

Note
01.8V--
13.3V--


Reference Designs

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In this Section you must refer to the Reference Design (Test board) for the particular module.

For Example: TE0728 Reference Designs

Notes

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In this Section you must refer to the Resources Page for the particular module.

For Example: TE0728 Resources





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Table of contents

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