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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEI0016 is a commercial-grade module based on Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tec0850tei0016-info for the current online version of this manual and other available documentation.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • ...
  • ....
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Block Diagram

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titleTExxxx block diagram
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  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C to 85°C

    • Package compatible device 10M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)

  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED 

  • Micro USB Connector

  • 16 Bit Analog to Digital Converter with 1 MSPS or 500 kSPS

  • 2x SMA Female Connector

  • I/O interface: 23x GPIO

  • Power Supply: 5V (from USB)

  • Dimension: 25 mm x 86.5 mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

Block Diagram

Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below

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    Note

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    Scroll Title
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    titleTExxxx main componentsTEI0016 block diagram


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    1. ...
    2. ...
    3. ...

    ...

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    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxtrue
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    diagramNameTEI0016_OV_BD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth641


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    Main Components

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    Notes :

    Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty

    • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below


    Note

    For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



    Scroll Title
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    titleInitial delivery state of programmable devices on the moduleTEI0016 main components


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    orientation

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    portrait

    border

    sortDirection

    false

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    viewerToolbar

    repeatTableHeaders

    true

    default

    fitWindow

    style

    false

    widths

    diagramDisplayName

    sortByColumn

    lbox

    1

    true

    sortEnabled

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    Storage device name

    Content

    Notes

    Quad SPI Flash

    		EEPROMDDR3 SDRAMSystem Controller CPLD

    Configuration Signals

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    • Overview of Boot Mode, Reset, Enables.

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    1. SMA Connector, J5...6
    2. Amplifier, U12
    3. Analog to Digital Converter, U6
    4. Voltage Reference, U8
    5. Voltage Regulator, U10 - U13 - U16
    6. Switching Voltage Regulator/LDO, U11 - U4
    7. SDRAM Memory, U2
    8. Intel® MAX 10 FPGA, U1
    9. SPI Flash Memory, U5 (not populated)
    10. 12.00 MHz MEMS oscillator, U7
    11. FTDI USB to JTAG/UART/FIFO, U3
    12. User LEDs, D2...9
    13. 4Kb EEPROM, U9
    14. Configuration LED (Red) , D10
    15. Power-on LED (Green), D1
    16. Push button, S1...2
    17. Micro USB Connector, J9
    18. 1x14 pin header, J2 (Not assembled)
    19. 1x6 pin header, J4 (Not assembled)
    20. Jumper, J3
    21. 1x14 pin header, J1 (Not assembled)

    Initial Delivery State

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    Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty


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    titleInitial delivery state of programmable devices on the module

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    titleBoot process.
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    MODE Signal State

    		Boot Mode
    Scroll Title
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    titleReset process.

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    Signal

    Storage device name

    		B2BI/ONote

    ...

    Content

    Notes

    Quad SPI Flash

    		N/A

    Not populated

    EEPROMProgrammed

    FTDI configuration


    Configuration Signals

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    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    Board to Board (B2B) I/Os

    ...

    • Overview of Boot Mode, Reset, Enables.

    The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

    FPGA Reconfigration can be triggered by pressing push button S1.

    Scroll Title
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    titleGeneral PL I/O to B2B connectors informationReset process.

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    FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes

    ...

    JTAG access to the TExxxx SoM through B2B connector JMX.

    ...

    anchorTable_SIP_JTG
    titleJTAG pins connection

    ...

    JTAG Signal

    ...

    B2B Connector

    ...

    MIO Pins

    ...

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    you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

    Example:

    Signal

    		Push ButtonPin HeaderNote

    RESET

    		S1J2Connected to nCONFIG


    Signals, Interfaces and Pins

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    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    I/Os on Pin Headers and Connectors

    Scroll Title
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    FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
    Bank 1AJ173.3VAIN0...6
    Bank 1BJ453.3VJTAG interface
    Bank 2J143.3VDIO2...5
    Bank 5J293.3VDIO6...14
    J123.3VDIO0...1
    Bank 8J213.3VRESET


    FPGA I/O Banks

    ...

    SPI_CS , SPI_DQ0... SPI_DQ3

    SPI_SCK

    ...

    anchorTable_OBP_MIOs
    titleMIOs pins

    ...

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    Notes :

    • add subsection for every component which is important for design, for example:
      • Two 100 Mbit Ethernet Transciever PHY
      • USB PHY
      • Programmable Clock Generator
      • Oscillators
      • eMMCs
      • RTC
      • FTDI
      • ...
      • DIP-Switches
      • Buttons
      • LEDs

    you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

    Example:

    MIO PinConnected toB2BNotes
    MIO12...14

    SPI_CS , SPI_DQ0... SPI_DQ3

    SPI_SCK

    		J2QSPI
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    Designator
    Scroll Title
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    titleOn board peripheralsFPGA I/O Banks

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    repeatTableHeadersdefault
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    FPGA BankI/O Signal CountConnected to
    		Chip/Interface
    Notes

    Quad SPI Flash Memory

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    anchorTable_OBP_SPI
    titleQuad SPI interface MIOs and pins
    Bank 1A71x14 Pin header, J1AIN0...6
    1Jumper, J3AIN7
    Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
    Bank 2


    		41x14 Pin header, J1D2...5
    5ADC, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
    112MHz Oscillator, U7CLK12M
    2Amplifier, U12nIAMP_A0, nIAMP_A1
    Bank 322SDRAM, U2RAM_ADDR_CMD
    Bank 59

    1x14 Pin header, J2

    		DIO6...14
    21x14 Pin header, J1DIO0...1
    1D12_RDIO12
    Bank 616SDRAM, U2DQ0...15
    2SDRAM, U2DQM0...1
    1D11_RDIO11
    Bank 8



    		8User Red LEDs, D2...9LED0...7
    6SPI Flash, U5F_CS, F_CLK, F_DI, F_DO, nSTATUS, DEVCLRn
    1Red LED, D10CONF_DONE
    6FTDI JTAG/UART Adapter, U3BDBUS0...5
    1Push Button, S2USER_BTN


    Micro-USB Connector

    The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.

    scroll-

    ...

    anchorTable_OBP_RTC
    titleI2C interface MIOs and pins

    ...

    anchorTable_OBP_I2C_RTC
    titleI2C Address for RTC

    ...

    scroll-title
    anchorTable_OBP_EEPUSB
    titleI2C EEPROM interface MIOs and Micro USB-2 connector pins

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    MIO Pin
    Pins
    		SchematicU?? PinNotes
    Connected toNote
    VBUSUSB_VBUS
    D+FTDI U3, DP pin
    D-FTDI U3, DM pin


    JTAG Interface

    JTAG access to the TEI0016 SoM through pin header connector J4.

    Scroll Title
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    titleJTAG pins connection
    Scroll Title
    anchorTable_OBP_I2C_EEPROM
    titleI2C address for EEPROM

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    MIO

    JTAG Signal

    Pin Header Connector

    I2C Address
    Note
    Designator
    TMS
    Notes
    J4-6

    ...

    scrolltitle

    TDI
    J4-
    5
    anchorTable_OBP_LED
    titleOn-board LEDs
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    SchematicColorConnected toActive LevelNote

    DDR3 SDRAM


    TDOJ4-4
    TCK

    J4-3


    JTAG_ENJ4-2Pulled-up to 3.3V.


    On-board Peripherals

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    Notes :

    Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

    The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

    • Part number: 
    • Supply voltage:
    • Speed: 
    • NOR Flash
    • Temperature: 

    ...

    • add subsection for every component which is important for design, for example:
      • Two 100 Mbit Ethernet Transciever PHY
      • USB PHY
      • Programmable Clock Generator
      • Oscillators
      • eMMCs
      • RTC
      • FTDI
      • ...
      • DIP-Switches
      • Buttons
      • LEDs


    Page properties
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    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


    Scroll Title
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    titleEthernet PHY to Zynq SoC connectionsOn board peripherals

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    BankSignal NameETH1ETH2Signal Description

    CAN Transceiver

    ...

    anchorTable_OBP_CAN
    titleCAN Tranciever interface MIOs
    Chip/InterfaceDesignatorNotes
    77530151U2
    FTDI FT2232HU3JTAG/UART/FIFO
    77530151U5
    77530151U9
    OscillatorU712 MHz clock source
    77530151U6Analog to Digital Converter
    8x User LEDsD2...9Red LEDs
    Push ButtonsS1...2


    SDRAM

    TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.

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    Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

    ...


    Scroll Title
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    titleOsillatorsSDRAM interface IOs and pins

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    DesignatorDescriptionFrequencyNote
    MHzMHzKHz

    Power and Power-On Sequence

    ...

    hiddentrue
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    In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

    • Power on-sequence
    • Power distribution
    • Voltage monitoring circuit
    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

    Power Supply

    Power supply with minimum current capability of xx A for system startup is recommended.

    Power Consumption

    ...

    anchorTable_PWR_PC
    titlePower Consumption

    ...

    * TBD - To Be Determined

    Power Distribution Dependencies

    ...

    anchorFigure_PWR_PD
    titlePower Distribution
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    SDRAM I/O Signals

    Signal Schematic Name

    		Connected toNotes
    Address inputs

    A0 ... A13

    		bank 3-
    Bank address inputs

    BA0 / BA1

    bank 3

    		-
    Data input/output

    DQ0 ... DQ15

    bank 6

    		-
    Data mask

    DQM0 ... DQM1

    bank 6

    		-
    ClockCLKbank 3-
    Control Signals

    CS

    bank 3

    		Chip select

    CKE

    bank 3

    		Clock enable

    RAS

    bank 3

    Row Address Strobe

    CAS

    bank 3

    Column Address Strobe

    WEbank 3Write Enable


    FTDI FT2232H

    The FTDI chip U3 converts signals from USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

    The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

    Scroll Title
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    titleFTDI chip interfaces and pins

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    FTDI Chip U3 PinSignal Schematic NameConnected toNotes
    ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
    ADBUS1TDIFPGA bank 1B, pin F5
    ADBUS2TDOFPGA bank 1B, pin F6
    ADBUS3TMS

    FPGA bank 1B, pin G1

    BDBUS0BDBUS0FPGA bank 8, pin A4User configurable
    BDBUS1BDBUS1FPGA bank 8, pin B4User configurable
    BDBUS2BDBUS2FPGA bank 8, pin B5User configurable
    BDBUS3BDBUS3FPGA bank 8, pin A6User configurable
    BDBUS4BDBUS4FPGA bank 8, pin B6User configurable
    BDBUS5BDBUS5FPGA bank 8, pin A7User configurable
    BDBUS6BDBUS6FPGA bank 6, pin C11
    BDBUS7BDBUS7FPGA bank 3, pin J7
    BCBUS0BCBUS0FPGA bank 5, pin J9
    BCBUS1BCBUS1FPGA bank 3, pin K5
    BCBUS2BCBUS2FPGA bank 3, pin K5
    BCBUS3BCBUS3FPGA bank 3, pin K5
    BCBUS4BCBUS4FPGA bank 3, pin K5


    SPI Flash

    Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

    Scroll Title
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    titleQuad SPI Flash memory interface

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    Signal Schematic NameConnected toNotes
    F_CSFPGA bank 8, pin B3Chip select
    F_CLKFPGA bank 8, pin A3Clock
    F_DIFPGA bank 8, pin A2Data in / out
    nSTATUS

    FPGA bank 8, pin C4

    		Data in / out, configuration dual-purpose pin of FPGA
    DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
    F_DOFPGA bank 8, pin B2Data in / out


    EEPROM

    The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

    Scroll Title
    anchorTable_OBP_EEP
    titleI2C EEPROM interface MIOs and pins

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    SchematicConnected toNotes

    EECS

    		FTDI U3, Pin EECS
    EECLKFTDI U3, Pin EECLK
    EEDATAFTDI U3, Pin EEDATA


    ADC

    The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS,
    boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 1MSPS.

    The ADC can be distinguished via its part code:

    • TEI0016-03-08-C8A: ADAQ7988BCCZ - 16-bit 500kSPS - starts with Y6H
    • TEI0016-03-08-C8B: ADAQ7980BCCZ - 16-bit 1.0MSPS - starts with Y6F
    Scroll Title
    anchorFigure_OV_BD
    titleTEI0016 part code variants


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    draw.io Diagram
    bordertrue
    viewerToolbartrue
    fitWindowfalse
    diagramNameTEI0016_part-code-variants
    simpleViewerfalse
    width600
    diagramWidth1922
    revision1


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    Scroll Title
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    titleADC converter interface and pins

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    PinsConnected toNotes

    IN+

    		U8, VOUT
    IN-U12, VOUT
    SDIBank 2, ADC_SDI
    SDOBank 2, ADC_SDO
    SCKBank 2, ADC_SCK
    CNVBank 2, ADC_CNV


    LEDs

    Scroll Title
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    titleOn-board LEDs

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    DesignatorColorConnected toActive LevelNote
    D2...9RedLED1...8Active HighUser LEDs
    D10RedCONF_DONEActive LowConfiguration DONE LED
    D1Green3.3V Power RailActive HighAfter power on it will be on.


    Push Buttons

    Scroll Title
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    titleOn-board Push Buttons

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    DesignatorConnected toFunctionalityNote
    S1RESETGeneral reset
    S2USER_BTNUser push buttonConnected to FPGA Bank 8.


    Clock Sources

    Scroll Title
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    titleOsillators

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    Clock SourceSchematic NameFrequencyNote
    MEMS Oscillator, U7CLK12M12.00 MHz

    Connected to FTDI FT2232 U3, pin 3.

    Connected to FPGA bank 2, pin H6.


    Power and Power-On Sequence

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    In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

    • Power on-sequence
    • Power distribution
    • Voltage monitoring circuit


    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


    Power Supply

    The module is supplied from USB (optionally via unpopulated pin header).

    Power Consumption

    Scroll Title
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    titlePower Consumption

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    FPGATypical Current
    Intel MAX 10 10M08 FPGATBD*


    * TBD - To Be Determined

    Power Distribution Dependencies

    Scroll Title
    anchorFigure_PWR_PD
    titlePower Distribution


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    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
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    simpleViewerfalse
    width
    linksauto
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    Power-On Sequence

    There is no specific or special power-on sequence, just one single power source is needed. After power on, the green LED (D1) will be on.

    Power Rails

    Scroll Title
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    titleModule power rails.

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    cellHighlightingtrue


    Power Rail Name

    Connector

    J2 Pin

    Connector

    J9 Pin

    		DirectionNotes
    VINJ2-13-Input5 V - Pin Header
    3.3VJ2-12-Output
    5VJ2-14-Output

    USB_VBUS

    		-J9-1Input5 V - USB Connector


    Bank Voltages

    Power-On Sequence

    ...

    anchorFigure_PWR_PS
    titlePower Sequency
    Scroll Ignore

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    Scroll Only

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    Voltage Monitor Circuit

    ...

    anchorFigure_PWR_VMC
    titleVoltage Monitor Circuit
    Scroll Ignore

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    ...

    Scroll Title
    anchorTable_PWR_PRBV
    titleModule power railsIntel Max 10 SoC bank voltages.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Power Rail Name

    B2B Connector

    JM1 Pin

    B2B Connector

    JM2 Pin

    B2B Connector

    JM3 Pin

    		DirectionNotes

    ...

    Bank          

    		Schematic Name

    Voltage

    		Notes
    Bank 1AVCCIO1A3.3V
    Bank 1B

    VCCIO1B

    		3.3V
    Bank 2VCCIO23.3V
    Bank 3VCCIO33.3V
    Bank 5VCCIO53.3V
    Bank 6VCCIO63.3V


    Bank 8VCCIO83.3V



    Technical Specifications

    Absolute Maximum Ratings

    Scroll Title
    anchorTable_PWRTS_BVAMR
    titleZynq SoC bank voltages.Absolute maximum ratings

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Bank          

    		Schematic Name

    Voltage

    		Notes

    ...

    hiddentrue
    idComments

    ...

    1
    sortEnabledfalse
    cellHighlightingtrue

    SymbolsDescriptionMinMaxUnitReference Document

    VIN 

    		Supply voltage4.755.25V
    CH1-, CH1+Analog input voltage on amplifier U12 pin 1, 10-3030VAD8251 datasheet

    T_STG

    		Storage Temperature-40+85°C



    Recommended Operating Conditions

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    Scroll Title
    anchorTable_TS_ROC
    titleRecommended operating conditions.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SymbolsMinMaxUnitReference Document
    VIN supply voltage (5.0V nominal)4.755.25V
    Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)-1010V
    T_OP0+70°CW9864G6JT-6 datasheet


    Physical Dimensions

    Module size: 86.5 mm × 25 mm.  Please download the assembly diagram for exact numbers.

    PCB thickness: 1.22 mm.

    Page properties
    hiddentrue
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    In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline"

    use "include page" macro and link to the general B2B connector page of the module series,

    ...

    ? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

    • 3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

      Operating Temperature: -??°C ~ ??°C
      Current Rating: ??A per ContactNumber of Positions: ??
      Number of Rows: ??

    Technical Specifications

    Absolute Maximum Ratings

    ...

    anchorTable_TS_AMR
    titlePS absolute maximum ratings

    ...

    Recommended Operating Conditions

    ...

    .



    Scroll Title
    anchorTableFigure_TS_ROCPD
    titleRecommended operating conditions.Physical Dimension


    scroll-
    tablelayout
    ignore
    orientation

    draw.io Diagram

    portrait

    border

    sortDirection

    false

    ASC

    viewerToolbar

    repeatTableHeaders

    true

    default

    fitWindow

    style

    false

    widths

    diagramDisplayName

    sortByColumn

    lbox

    1

    true

    sortEnabled

    revision

    false

    2

    cellHighlightingtrue
    ParameterMinMaxUnitsReference Document
    VSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.

    Physical Dimensions

    • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: ? mm.

    ...

    diagramNameTEI0016_TE_PD
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth641


    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Image Added


    Currently Offered Variants 

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .
    Page properties
    hiddentrue
    idComments

    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    if not available, set.

    In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://wwwfileadmindocs_/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
    Note


    Scroll Title
    anchorFigureTable_TSVCP_PDSO
    titlePhysical DimensionTrenz Electronic Shop Overview

    scroll-

    ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Currently Offered Variants 

    ...

    hiddentrue
    idComments

    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    if not available, set.

    tablelayout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Trenz shop TEI0016 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

    Scroll Title
    anchorTable_RH_HRH
    titleHardware Revision History

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DateRevisionChangesDocumentation Link
    2019-02-1101-REV01


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    ...

    https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/

    ...

    Scroll Title
    anchorTableFigure_VCPRV_SOHRN
    titleTrenz Electronic Shop Overview Board hardware revision number.


    scroll-
    tablelayout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    Trenz shop TE0728 overview page
    English pageGerman page

    Revision History

    Hardware Revision History

    List of online PCN ...Link

    ...

    anchorTable_RH_HRH
    titleHardware Revision History
    ignore

    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxtrue
    revision1
    diagramNameTEI0016_RV_HRN
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth154


    Scroll Only
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue

    Image Added


    ...

    Document Change History

    Page properties
    hiddentrue
    idComments
    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following

      • Add new row below first

      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports

    ...

    Scroll Title
    anchorTable_RH_DCH
    titleDocument change history.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DateRevisionContributorDescription

    Page info
    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    prefixv.
    typeFlat
    showVersionsfalse

    Page info
    infoTypeModified by
    typeFlat
    showVersionsfalse

    change list
    • major cleanup multiply sections

    2019-09-20

    		v.56Kilian Jahn
    • update notes for variants
    2019-06-05v.55ED

    • Technical Specifications updated

    • Power Rails updated

    --

    all

    Page info
    infoTypeModified users
    typeFlat
    showVersionsfalse

    • --


    ...