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Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board" Date | Version | Changes | Author |
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2023-09-13 | 2.3 | - update to 22.x
- "select COM Port" → Linux command changed
| TD | 2022-06-15 | 2.2 | - add 'QSPI-Boot mode'
- add 'Get prebuilt boot binaries'
- changed SD-Boot mode chapter
- 'Device Tree' chapter expanded
| TD | 2022-04-21 | 2.1 | | TD | 2022-02-28 | 2.0 | - add yocto to
- Overview → Key Features
- Overview → Requirements
- Design Flow
- Launch
- add section 'Software Design - Yocto'
| TD | 2021-06-15 | 1.2 | - table of content view
- template history
- placed a horizontal separation line under each chapter heading
- replaced <design name> by <project folder>
- changed title-alignment for tables from left to center
- update 19.x to 20.x
| JH,TD | 2020-11-24 | 1.1 | - add fix table of content
- add table size as macro
| JH | -- | 1.0 | -- | -- |
|
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Important General Note: Export PDF to download, if quartus revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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Refer to http://trenz.org/te0xyztei0050-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - Add basic key futures, which can be tested with the design
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Excerpt |
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- Quartus Prime Pro 21Lite 23.41std
- Yocto
- NIOS IIV/m
- UART
- ETH
- USB
- I2C
- QSPI flash
- DDR3 memory
- User LED
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Revision History
- SDRAM controller (AXI4)
- User LED
- User button
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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title | Design Revision History |
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repeatTableHeaders | default |
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Date | Quartus | Project Built | Authors | Description |
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20220421214 ProTEI0006214020220421183824TEI0006214020210421183915Thomas Dück | | |
Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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title | Known Issues |
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Ruoshui Chen | - updated to Quartus Lite 23.1std
- reconstruct pmw and mux code to optimize RTL synthesis
| 2024-05-17 | 22.1 Lite | TEI0050-test_board_noprebuilt-quartus_22.1std.2-20240517115737.zip TEI0050-test_board-quartus_22.1std.2-20240517115802.zip | Thomas Dück | - update to Quartus Lite 22.1std
- change to Nios V/m
- TE scripts update
| 2023-02-13 | 21.1.1 Lite | TEI0050-test_board_noprebuilt-quartus_21.1.1-20230213145533.zip TEI0050-test_board-quartus_21.1.1-20230213145613.zip | Thomas Dück | - fixed BSP_DIR in software project
| 2022-08-11 | 21.1.1 Lite | TEI0050-test_board_noprebuilt-quartus_21.1.1-20220811093744.zip TEI0050-test_board-quartus_21.1.1-20220811093807.zip | Thomas Dück | |
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Release Notes and Know Issues
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
Requirements
Software Page properties |
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixedlist of software which was used to generate the design
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anchor | Table_SWKI |
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title-alignment | center |
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title | SoftwareKnown Issues |
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orientation | portrait |
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SoftwareVersionNote | Quartus Prime Pro | 21.4 | needed | NIOS II SBT for Eclipse | --- | optional | Yocto | dunfell | optional (more information: Yocto KICKstart#Used source files) | SI ClockBuilder Pro | Workaround | To be fixed version |
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No known issues | --- | --- | --- | optional
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Requirements
HardwareSoftware
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Notes : - list of hardware software which was used to generate the design
- mark the module and carrier board, which was used tested with an *
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Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title-alignment | center |
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title | Hardware ModulesSoftware |
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orientation | portrait |
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Module Model | Board Part Short Name | Yocto Machine Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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*used as reference
Design supports following carriers:
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anchor | Table_HWC |
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title-alignment | center |
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title | Hardware Carrier |
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Software | Version | Note |
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Quartus Prime Lite | 23.1std | Nios V license is needed. For more information see: Intel Nios V Processors | RiscFree IDE for Intel FPGAs | 23.1std | needed |
|
Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title-alignment | center |
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title | Hardware Modules |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Carrier Model | Notes |
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--- | *used as reference
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
*used as reference
Content
For general structure and usage of the reference design, see Project Delivery - Intel devices
Design Sources
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TEI0050-01-AAH11A | AH11 | REV01 | 8MByte | 2MByte | -- | -- | TEI0050-01-AAH13A* | AH13 | REV01 | 8MByte | 8MByte | -- | -- |
*used as reference |
Design supports following carriers:
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anchor | Table_HWC |
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title-alignment | center |
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title | Hardware Carrier |
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anchor | Table_DS |
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title-alignment | center |
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title | Design sources |
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orientation | portrait |
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cellHighlighting | true |
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Type | LocationQuartus | <project folder>/source_files/quartus <project folder>/source_files/<Board Part Short Name>/quartus | Quartus project will be generated by TE Scripts (Optional) Source files for specific assembly variants | Software | <project folder>/source_files/software <project folder>/source_files/<Board Part Short Name>/software | Additional software will be generated by TE Scripts (Optional) Source files for specific assembly variants | Yocto | <project folder>/source_files/os/yocto | Yocto BSP layer template for linux | |
Prebuilt
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - Intel devices
Design Sources
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anchor | Table_DS |
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title-alignment | center |
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title | Design sources |
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Notes : prebuilt filesTemplate Table: Scroll Title |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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1 | sortEnabled | false |
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cellHighlighting | true |
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FileFile-ExtensionDescriptionSOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware |
SRAM Object File | *.sof | Ram configuration file |
Programmer Object File | *.pof | FPGA configuration file |
JTAG Indirect Configuration file | *.jic | Flash configuration file |
Raw binary file | *.rbf | FPGA configuration file |
Diverse Reports | --- | Report files in different formats |
Software-Application-File | *.elf | Software application for NIOS II processor system |
Device Tree | *.dtb | Device tree blob |
SFP-File | *.sfp | Boot image with SPL (Secondary Program Loader) |
BIN-File | *.bin | Image with linux kernel and ram disk |
CONF-File | *.conf | Boot configuration file (extlinux.conf) |
Yocto linux image | *.wic | Linux image for SD card |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware |
SRAM Object File | *.sof | Ram configuration file |
JTAG indirect configuration file | *.jic | Flash configuration file |
Raw binary file | *.rbf | FPGA configuration file |
Diverse Reports | --- | Report files in different formats |
Software-Application-File | *.elf | Software application for NIOS II processor system |
Download
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
Open create_project_win.cmd/create_project_linux.sh:
Image RemovedSelect Board in "Board selection"Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
Create and configure your Yocto Linux project, see Yocto KICKstartCopy the generated meta-<module> folder from <project name>/os/yocto/meta-<module> to the path/to/yocto/poky/ directoryFollow the steps from Yocto KICKstart#Create a project for an Intel FPGA device without running the 'bitbake' commandAdd the generated bsp layer meta-<machine> to path/to/yocto/poky/build/conf/bblayers.conf with:
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bitbake-layers add-layer ../meta-<module> |
Info |
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Note: The generated meta-<module> layer depends on the meta-altera layer (for more information see: Yocto KICKstart#Used source files), so you need to add both bsp layers to bblayers.conf |
Redefine the variable MACHINE with '<module>-<Board-Part-Short-Name>' in path/to//yocto/poky/build/conf/local.conf. The correct MACHINE name can be found in the #Hardware table.
Also define the variables INITRAMFS_IMAGE_BUNDLE and INITRAMFS_IMAGE to generate a ram disk image.
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sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf
echo -e '\nMACHINE = "<module>-<Board-Part-Short-Name>"' >> conf/local.conf
echo -e '\nINITRAMFS_IMAGE_BUNDLE = "1"' >> conf/local.conf
echo -e 'INITRAMFS_IMAGE = "te-initramfs"' >> conf/local.conf |
Build the image with following command (the image recipes are located in meta-<module>/recipes-core/images/):
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bitbake te-image-minimal |
Launch
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Note: - Programming and Startup procedure
|
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Get prebuilt boot binaries
Note |
---|
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
- Run create_project_win.cmd/create_project_linux.sh
- Select Module in 'Board selection'
- Click on 'Export prebuilt files' button
- Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened
SD-Boot mode
Prepare SD card as follows for SD-BootRun following command to get the device name of the SD card (e.g. /dev/sdx):
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lsblk |
Insert SD card in the SD card reader, unmount and erase it Code Block |
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sudo umount /dev/sdx
sudo sfdisk --delete /dev/sdx |
Create required partitions on the SD card (partition 1: 50MB, FAT32 / partition 2: 2MB, a2)
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echo -e ',50M,c\n,2M,a2' | sudo sfdisk /dev/sdb --force
sudo mkfs.vfat -F 32 -n boot /dev/sdb1 |
Copy the u-boot file to partition 2 of the SD card
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sudo dd if=path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp of=/dev/sdb2 bs=1M seek=0
sync
|
Copy zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ via file manager to the partition 1 (named 'boot') on SD cardSet Boot Mode to SD-Boot- Depends on Carrier, see carrier TRM
Insert SD-Card in the SD-SlotQSPI-Boot mode
Option for u-boot-with-spl.sfp on QSPI flash and zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and extlinux/extlinux.conf on SD card.
Use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: #Get prebuilt boot binaries
Connect JTAG and power on carrier with moduleOpen path/to/intelFPGA_lite/21.1/embedded/Embedded_Command_Shell.bat ( Win OS)/path/to/intelFPGA_lite/21.1/embedded/embedded_command_shell.sh (Linux OS) from Intel SoC FPGA EDSRun following commands:
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quartus_hps -c 1 -o pv -a 0x0 path/to/_binaries_<Article Name>/boot_linux/u-boot-with-spl.sfp |
Copy zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ to SD card.Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM
Insert the SD card in the SD-SlotQSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd/create_project_linux.sh
- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this example.
Usage
- Prepare HW like described on section TEI0050 Intel Test Board
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
Open Serial Console (e.g. PuTTY)select COM Port
Info |
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Win OS: see device manager Linux OS: see dmesg | grep tty (UART is *USB1) |
Speed: 115200Press reset buttonConsole output depends on used Software project, see Software Design - SDK#ApplicationLinux Console:Login data:
Info |
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Note: Wait until Linux boot finished |
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Username: root
Password: root |
You can use Linux shell now.
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i2cdetect -y -r 1 (check I2C 1 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check) |
Quartus | <project folder>/source_files/quartus | Quartus project will be generated by TE Scripts | Software | <project folder>/source_files/software | Additional software will be generated by TE Scripts |
|
Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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| Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
File | File-Extension | Description |
---|
SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware | SRAM Object File | *.sof | Ram configuration file | Programmer Object File | *.pof | FPGA configuration file | JTAG Indirect Configuration file | *.jic | Flash configuration file | Raw binary file | *.rbf | FPGA configuration file | Diverse Reports | --- | Report files in different formats | Software-Application-File | *.elf | Software application for NIOS II processor system | Device Tree | *.dtb | Device tree blob | SFP-File | *.sfp | Boot image with SPL (Secondary Program Loader) | BIN-File | *.bin | Image with linux kernel and ram disk | CONF-File | *.conf | Boot configuration file (extlinux.conf) | Yocto linux image | *.wic | Linux image for SD card |
|
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
---|
SOPC Information File | *.sopcinfo | File with description of the .qsys file to create software for the target hardware | SRAM Object File | *.sof | Ram configuration file | JTAG indirect configuration file | *.jic | Flash configuration file | Diverse Reports | --- | Report files in different formats | Software Application File | *.elf | Software application for Nios V processor system |
|
Download
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
Design Flow
Scroll Ignore |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
---|
|
|
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
- Open create_project_win.cmd/create_project_linux.sh:
Image Added - Select Board in "Board selection"
- Click on "Create project" button to create project
- (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
Launch
Page properties |
---|
|
Note: - Programming and Startup procedure
|
Programming
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Get prebuilt files
Note |
---|
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
- Run create_project_win.cmd/create_project_linux.sh
- Select Module in 'Board selection'
- Click on 'Export prebuilt files' button
- Folder <project folder>/_binaries_<Article Name> with subfolder programming_files will be generated and opened
QSPI
- Connect JTAG and power on carrier with module
- Open create_project_win.cmd/create_project_linux.sh
- Select correct board in "Board selection"
- Click on "Program device" button
- if prebuilt files are available: select "Program prebuilt file"
- using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
- (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
- Click on "Start program device" button
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
UART
- Open Serial Console (e.g. PuTTY)
select COM Port
Info |
---|
Win OS: see device manager Linux OS: see ls -l dev/serial/by-id (UART is *USB1) |
- Speed: 115200
- Press reset button S1
- Press user button S2 to toggle between different LED sequences
- Console output depends on used Software project, see Software Design - SDK#Application
System Design - Quartus
Block Design
The block designs may differ depending on the assembly variant.
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title-alignment | center |
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title | Block Design - Project |
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title-alignment | center |
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title | Block Design - Platform Desginer |
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Image Added |
Software Design - SDK
Application
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---------------------------------------------------------- General Example: hello_tei0006 Hello TEI0006 is a Hello World example as endless loop instead of one console output. |
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
test_tei0050
'test_tei0050' prints the current mode of the LEDs in console.
...System Design - Quartus
Scroll Ignore |
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Block Design
The block designs may differ depending on the assembly variant.
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Project |
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|
>>Project<< |
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design - Platform Desginer |
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|
>>Platform Designer<< |
HPS Interfaces
Activated interfaces:
Type | Note |
DDR | -- |
EMAC0 | -- |
EMAC1 | -- |
GPIO0 | -- |
GPIO1 | -- |
GPIO2 | -- |
I2C0 | -- |
I2C1 | -- |
QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB0 | -- |
USB1 | -- |
CAN0 | -- |
CAN1 | -- |
Software Design - SDK
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Application
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---------------------------------------------------------- General Example: hello_tei0006Hello TEI0006 is a Hello World example as endless loop instead of one console output. |
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
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Software Design - Yocto
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For Yocto installation and project creation, follow instructions from:
U-Boot
Start with Create a custom BSP layer for Intel SoC or FPGA#Configure u-boot
File location: meta-<module>/recipes-bsp/u-boot/
Changes:
Device Tree
U-boot Device Tree
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#u-boot device_tree.dts
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title | Excerpts from test_board/os/yocto/meta-<module_series>/recipes-bsp/u-boot/files/<module_series>_<Board_Part_Short_Name>/dts/<module_series>_<Board_Part_Short_Name>-u-boot.dts |
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#device_tree-u-boot.dts
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};
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Kernel Device Tree
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title | Excerpts from test_board/os/yocto/meta-<module_series>/recipes-kernel/linux/files/dts/<module_series>_<Board_Part_Short_Name>.dts |
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#kernel device_tree.dts
/ {
};
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Kernel
Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernelFile location: meta-<module>/recipes-kernel/linux/
Changes:
Images
Image recipe for minimal console image
File location: meta-<module>/recipes-images/yocto/
Image recipes:
- te-image-minimal.bb: create minimal linux image
- te-initramfs.bb: required for building an image with initial RAM Filesystem
Added packages/recipes:
Rootfs
Used filesystem: Initial RAM Filesystem (initramfs)
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
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Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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title | Document change history |
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| | - update to Quartus Prime Lite 23.1
| 2024-05-17 | v.7 | Thomas Dück
| - update to Quartus Prime Lite 22.1
- document style update
| 2023-02-14 | v.6 | Thomas Dück | - fixed BSP_DIR in software project
| 2022-08-11 | v.5 | Thomas Dück | | change list | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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Legal Notices
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