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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Table of contents

Table of Contents
outlinetrue

Overview

CPLD Device with designator U3: LCMX02-256HC

Feature Summary

  • Power Management
  • FPGA, USB Reset Managment
  • JTAG routing

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
3.3V / PG_SENSEin25 Power Sense
DONE        in28 FPGA Done Pin
EN1         in11 Enable Pin From B2B
F_TCK        out17 JTAG from/to FPGA
F_TDI        out23 JTAG from/to FPGA
F_TDO / C_TDO     in9 JTAG from/to FPGA
F_TMS        out10 JTAG from/to FPGA
FPGA_IO1 / FPGA_IO  IO1 in21 FPGA Pin
FPGA_IO2     20 / currently_not_used
FTDI_RESET_N out5 USB FTDI Reset
JTAGEN       in26 Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)
MODE         in13 / currently_not_used
NOSEQ        inout14 / currently_not_used
PG_DDR_PWR / PG_DDRin4 Power Good from DDR
PGOOD        out12 Power Good to B2B
PROG_B      inout27 FPGA PROG_B
RESIN        in16 Reset Pin From B2B
SYSLED1 out8 LED (Green)
TCK    TCK  / M_TCK      in30 JTAG from/to B2B
TDI / M_TDIin32 JTAG from/to B2B
TDO          out1 JTAG from/to B2B
TMS  / M_TMSin29 JTAG from/to B2B

 

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).

Power

Power Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).

Reset

PROG_B is set to one, if power is good.

FTDI_RESET_N is set to one, if power is good.

LED

LEDDescription
SYSLED1 (Green LED D1)ON when RESIN=0, else FGPIO1 when DONE=1 else Blinking

Appx. A: Change History

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Revision Changes

Document Change History

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Appx. B: Legal Notices

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IN:Legal Notices
IN:Legal Notices

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