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Feature Summary

  • Power Management...
  • Boot Mode
  • Reset
  • UART

  • IO Expender(RGPIO)

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription
BM2
/MIO4   
/MIO4   / BM2_MIO4outB353.3VBoot Mode Pin to FPGA (SD or QSPI)
BOOTMODE   outB323.3V
CONFIGX    
B2B UART from MIO15
CONFIGX  inB333.3VB2B UART to MIO14
CPLD_GPIO0 
A33.3VB2B / currently_not_used
CPLD_GPIO1 
B13.3VB2B / currently_not_used
CPLD_GPIO2 
A13.3VB2B / currently_not_used
CPLD_GPIO3 inA23.3V
DONE       
B2B, used for Boot Mode
DONE inA353.3VFPGA Done signal
EN_
1V      
1VoutB33.3Vdisable/enable module power 1V and all other related voltages
EXT_
IO1    
IO1inoutA33EXT_IO_VCCB2B, RGPIO /
EXT_
IO10   
IO10 inoutB22EXT_IO_VCCB2B, RGPIO
EXT_
IO11   
IO11 inoutA24EXT_IO_VCCB2B, RGPIO
EXT_
IO12   
IO12 inoutA23EXT_IO_VCCB2B, RGPIO
EXT_
IO13   
IO13 inoutB21EXT_IO_VCCB2B, RGPIO
EXT_
IO14   
IO14 inoutA28EXT_IO_VCCB2B, RGPIO
EXT_
IO15   
IO15 inoutB18EXT_IO_VCCB2B, RGPIO
EXT_
IO16   
IO16 inoutA22EXT_IO_VCCB2B, RGPIO
EXT_
IO17   
IO17 inoutB8EXT_IO_VCCB2B, RGPIO
EXT_
IO18   
IO18 inoutA9EXT_IO_VCCB2B, RGPIO
EXT_
IO19   
IO19 inoutA20EXT_IO_VCCB2B, RGPIO
EXT_
IO2    
IO2inoutB24EXT_IO_VCCB2B, RGPIO
EXT_
IO20   
IO20 inoutB14EXT_IO_VCCB2B, RGPIO
EXT_
IO21   
IO21 inoutA8EXT_IO_VCCB2B, RGPIO
EXT_
IO22   
IO22 inoutB7EXT_IO_VCCB2B, RGPIO
EXT_
IO23   
IO23 inoutB13EXT_IO_VCCB2B, RGPIO
EXT_
IO24   
IO24 inoutA18EXT_IO_VCCB2B, RGPIO
EXT_
IO25   
IO25 inoutA5EXT_IO_VCCB2B, RGPIO
EXT_
IO26   
IO26 inoutB4EXT_IO_VCCB2B, RGPIO
EXT_
IO27   
IO27 inoutA13EXT_IO_VCCB2B, RGPIO
EXT_
IO28   
IO28 inoutA17EXT_IO_VCCB2B, RGPIO
EXT_
IO29   
IO29 inoutA6EXT_IO_VCCB2B, RGPIO
EXT_
IO3    
IO3inoutA27EXT_IO_VCCB2B, RGPIO
EXT_
IO30   
IO30 inoutB5EXT_IO_VCCB2B, RGPIO
EXT_
IO31   
IO31 inoutB12EXT_IO_VCCB2B, RGPIO
EXT_
IO32   
IO32 inoutA16EXT_IO_VCCB2B, RGPIO
EXT_
IO33   
IO33 inoutA7EXT_IO_VCCB2B, RGPIO
EXT_
IO34   
IO34 inoutB9EXT_IO_VCCB2B, RGPIO
EXT_
IO35   
IO35 inoutA15EXT_IO_VCCB2B, RGPIO
EXT_
IO36   
IO36 inoutB15EXT_IO_VCCB2B, RGPIO
EXT_
IO37   
IO37 inoutA11EXT_IO_VCCB2B, RGPIO
EXT_
IO38   
IO38 inoutA12EXT_IO_VCCB2B, RGPIO
EXT_
IO39   
IO39 inoutB16EXT_IO_VCCB2B, RGPIO
EXT_
IO4    
IO4inoutB20EXT_IO_VCCB2B, RGPIO
EXT_
IO40   
IO40 inoutA21EXT_IO_VCCB2B, RGPIO
EXT_
IO5    
IO5inoutA31EXT_IO_VCCB2B, RGPIO
EXT_
IO6    
IO6inoutB23EXT_IO_VCCB2B, RGPIO
EXT_
IO7    
IO7inoutA26EXT_IO_VCCB2B, RGPIO
EXT_
IO8    
IO8inoutA25EXT_IO_VCCB2B, RGPIO
EXT_
IO9    
IO9inoutA30EXT_IO_VCCB2B, RGPIO
FPGA_CPLD1 inA403.3VFPGA AB19, RGPIO CLK
FPGA_CPLD2 outB283.3VFPGA AB20, RGPIO out
FPGA_CPLD3 inA383.3VFPGA AD20, RGPIO in
FPGA_CPLD4 inA363.3VFPGA AE20 goes to LED2
JTAGENBinB303.3VEnable CPLD JTAG access, otherwise M_... is used as GPIO
LED2outB10EXT_IO_VCCStatus LED D1 red
M_
TCK      
TCKinA453.3VJTAG if JTAGENB is high/ currently_not_used
M_
TDI      
TDIinA473.3VJTAG if JTAGENB is high/ currently_not_used
M_
TDO      
TDOoutA483.3VJTAG if JTAGENB is high/ currently_not_used
M_
TMS      
TMSinB343.3V
MIO14      
JTAG if JTAGENB is high/ currently_not_used
MIO14outA443.3V
MIO15      
UART out to FPGA
MIO15inA423.3VUART in from FPGA 
nRST_
IN    
INinA323.3VReset from B2B to PS_POR
PG_ALLinA463.3VStatus power
PROG_
B     A41
B inB253.3VStatus PROG_B/ currently_not_used
PS_
POR     
POR inoutA413.3Vopen drain as second reset from nRSR_IN/ currently_not_used
NC
B293.3Vdummy pin / not connected
NC
B27
3.3Vnot connected
NC
A343.3Vnot connected


Functional Description

JTAG

Set JTAGENB(J3-136) high to get access to CPLD via JTAG, otherwise CPLD JTAG Pins can be used as GPIO.

Power

EN_1V is set to constant high.

Boot Mode

CPLD_GPIO3 (J2-16) is used to set boot Mode Pin BM2_MIO4. Signal is inverted to be compatible with second XMOD on TEBT0782

J2-16Description
lowSD Boot*
highQSPI (default)

* not supported with TEBT0782

Reset

nRST_IN drive POR_B as open drain.

U27(TPS3106) or nRST_IN can reset Zynq.

UART

MIO14 is connected to CONFIGX.

BOOTMODE is connected to MIO15.

RGPIO (beta)

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes. System need RGPIO IP on FPGA side.

  • RGPIO CLK is  FPGA_CPLD1 (up to 50MHz).
  • Output is FPGA_CPLD2
  • Input is FPGA_CPLD3
RGPIO from FPGADescription
0...19Connected to EXT_IO(even numbers), if RGPIO is activated, otherwise EXTIO is high impedance
20...23Connected to RGPIO 20...23, if RGPIO is activated.
24...27Reserved
28...31Activation code from FPGA. Must match "1010"
RGPIO to FPGADescription
0...19Connected to EXT_IO(odd numbers)
20...23RGPIO 20...23 from FPGA, if RGPIO is activated, otherwise zero
24...27Reserved
28...31Activation code to FPGA. Must match "1010"


LED

LED2 D1 Red
PriorityBlink SequenceComment
1********PG_ALL, Power problem
2*****oooPROG_B, SoC PROGAM_B down
3****ooooPS_POR, SoC PS_POR_B down
4***oooooDONE, SoC DONE down
5user definedFPGA_CPLD4 connected to LED

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision  revision got to "Change History"   of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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prefixv.



REV01REV01

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Work in progress


  • typo correction

v.9REV01REV01John Hartfiel
  • Revision 01 finished
2018-05-28

v.1

REV01REV01

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  • Initial release

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