Page History

Overview

TE0729 Basic-System with Watchdog example via VIO Interface.
Refer to http://trenz.org/te0729-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of AMD Software for the same Project.

Reference Design is available on:

• TE0729 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on AMD Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by AMD Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"
3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Vitis install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. (Optional) Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

7. Generate Programming Files with Vitis (recommended)
   1. Copy PetaLinux build image files to prebuilt folder

      • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        

        Info
        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

        
        

        Page properties
        hidden true id Comments
        This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for Microblaze ...

        
        

   2. Generate Programming Files with Vitis

      Code Block
      language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      
      

      Note
      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

      
      

8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Programming

AMD documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection
   3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0820 (optional)

   
   

3. Copy image.ub and boot.scr on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
4. Set Boot Mode to QSPI-Boot and insert SD
   
   • Depends on Carrier, see carrier TRM.
5. insert SD-Card.

SD-Boot mode

1. Copy image.ub, boot.scr and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. Power On PCB

   Expand
   title boot process
   1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze with Linux 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ...

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

2. Linux Console(not needed if autologin activated):
   

   Code Block
   language bash theme Midnight
   # password disabled petalinux login: root Password: root

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)

4. Optional Features

   • Webserver to get access to Zynq
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
  • "WDI_EN" and "WDI_HIT_*_EN_CLK" enables FPGA watchdog control.
  • Force WD to system reboot:
    1. Check on Hardware window VIO status is ok. (right click on vio symbol and click "commit output values to VIO core" for update).
    2. Enable one of the "WDI_HIT_*_EN_CLK" signals
    3. Enable "WDI_EN"
    4. To force system to reboot, disable WDI_HIT clocks.
• Monitoring:
  • Set radix for "fm_*" signals to unsigned integer to see frequ in Hz. PSFCLK0 50MHz was increased to 100MHz with version update 2023.2
  • "fm_*" shows some clk frequencies (unit Hz). Note: inaccurate Reference CLK is used for frequency measurement.

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title Block Design
Image Added

PS Interfaces

Constraints

Basic module constraints

#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

#
# Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN
#

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design]

Design specific constraints

set_property PACKAGE_PIN F16 [get_ports {FPGA_IO[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_IO[0]}]
set_property PACKAGE_PIN H15 [get_ports {WDI_EN[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WDI_EN[0]}]
set_property PACKAGE_PIN R15 [get_ports {WD_HIT[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {WD_HIT[0]}]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Source location: \sw_lib\sw_apps

zynq_fsbl

TE modified 2023.2 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  • Optional define for eMMC selection with FSBL (default SD selected)
    • uncomment #define USE_EMMC on te_fsbl_hooks_te0729.h to select eMMC instead of SD

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0729

Hello TE0729 is a Vitis Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. VitisI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

The project folder contains a folder named "os". This is a template for the TE0729 petalinux project with all necessary changes applied. You can just add the XSA file and build the project to get working binaries.

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x0100000
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_SIZE=0x1400000
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0x0020000
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x40000

U-Boot

Start with petalinux-config -c u-boot

Changes:

• CONFIG_ENV_OVERWRITE=y

Boot Modes:

• CONFIG_QSPI_BOOT=y
• CONFIG_SD_BOOT=y
• CONFIG_BOOT_SCRIPT_OFFSET=0x1520000  
  (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)

Device Tree

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};
 
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
 
 

Kernel

Start with petalinux-config -c kernel

Changes:

• CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

• For web server app:
  • CONFIG_busybox-httpd=y
• For additional test tools only:
  • CONFIG_i2c-tools=y
  • CONFIG_packagegroup-petalinux-utils=y      (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y
• For usage of phytool:
  • CONFIG_ethtool=y
• For auto login:
  • CONFIG_auto-login=y 

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Core

To enable dhcp for all ethernet interfaces create path like: see "<project folder>\os\petalinux\project-spec\meta-user\recipes

-core\init-ifupdown"

in petalinux build directory. Documented here Petalinux Yocto tips under " Method 2 : use your own interfaces file".

Additional Software

No additional software is needed.

App. A: Change History and Legal Notices

Document Change History

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