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Table of Contents |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEP0006 is an Ultra96 LS Expansion to Pmod adapter.
Refer to http://trenz.org/tec0850tep0006-info for the current online version of this manual and other available documentation.
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups: - FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- FPGAOn Board:
- Package:
- Speed:
- Temperature:
- RAM/Storage:
- On Board:
- Interface:
- Power:
- Dimension:
- 4x Voltage Level Translators
- 2x Voltage Regulators
- Interface:
- 1x Ultra96 LS Expansion Header (40 Pins)
- 3x Pmod Connectors
- 3x Jumpers
- Power:
- Dimension:
Block Diagram
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anchor | Figure_OV_BD |
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title | TExxxx TEP0006 block diagram |
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Main Components
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title | TExxxx main componentsTEP0006 Main Components |
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- ...
- ...
- ...
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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- PMod 2x6 Host Socke (PMOD 2) ,J2
- PMod 2x6 Host Socke (PMOD 2) ,J1
- Level Translator (HP_GPIO[0..7]) ,U1
- Level Translator (HP_GPIO[8..15]),U3
- Level Translator PMOD(SPI),U6
- Linear Voltage Regulator,U2
- Jumper,J6-J7
- PMod 2x6 Host Socke (SPI),J4
- GROVE,J5
- Level Translator (GROVE) ,U5
- Jumper (Voltage select ),J10
- Ultra96 LS Expansion Header (40 Pos),J3
Initial Delivery State
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Storage device name
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Content
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Notes
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Quad SPI Flash
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Configuration Signals
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty Overview of Boot Mode, Reset, Enables. |
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anchor | Table_OV_BPIDS |
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title | Boot process.Initial delivery state of programmable devices on the module |
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MODE Signal State | Boot Mode |
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal | B2B | I/O | Note |
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Storage device name | Content | Notes |
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--- | --- | --- |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
Low Speed Expansion Connector
The SMD Header J3 has 40 pin (20x2) and it is compatible with Ultra96 LS Expansion Connector. You can find General information about the LS Expansion connector in the following table.FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2BUltra96 |
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title | General PL I/O to B2B connectors Ultra96 LS Expansion information |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
Schematic | Connected to | Notes |
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HD_GPIO0...7 | Level Translator HP_GPIO[0...7], U1 | GPIO0...7 | HD_GPIO8...15 | Level Translator HP_GPIO[8...15], U3 | GPIO8...15 | MIO36...37 | Level Translator PMOD(SPI) | PS_GPIO_0...1 | MIO38, MIO41...43 | Level Translator PMOD(SPI) | SPI | VCC_PSAUX | Level Translator, U1-U3-U5-U6 Voltage Regulator, U2 | 1.8 V nPOK | 5V | Voltage Regulator, U2 Jumper, J10 | Vin Pull up Voltage |
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Pmod Connectors
The TEP0006 is equipped with three Pmod connectors. Pmod Connectors are the expanded outputs from Ultra96 Board.
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anchor | Table_SIP_Pmod |
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title | Pmod Connectors information |
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Pin | Connected to | Notes |
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Pmod 1, J1 | Pmod 2, J2 | Pmod SPI, J4 |
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1 | PMOD_HD-GPIO0 | PMOD_HD-GPIO8 | SS |
| 2 | PMOD_HD-GPIO1 | PMOD_HD-GPIO9 | MOSI |
| 3 | PMOD_HD-GPIO2 | PMOD_HD-GPIO10 | MISO |
| 4 | PMOD_HD-GPIO3 | PMOD_HD-GPIO11 | SCK |
| 5 | GND | GND | GND |
| 6 | 3.3 V | 3.3 V | 3.3 V |
| 7 | PMOD_HD-GPIO4 | PMOD_HD-GPIO12 | INIT |
| 8 | PMOD_HD-GPIO5 | PMOD_HD-GPIO13 | RESET |
| 9 | PMOD_HD-GPIO6 | PMOD_HD-GPIO14 | Not Connected |
| 10 | PMOD_HD-GPIO7 | PMOD_HD-GPIO15 | Not Connected |
| 11 | GND | GND | GND |
| 12 | 3.3 V | 3.3 V | 3.3 V |
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Jumpers
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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anchor | Table_OBP_MIOs |
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title | MIOs pins |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes :
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anchor | Table_SIP_OBPPmod |
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title | On board peripheralsPmod Connectors information |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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anchor | Table_OBP_I2C_RTC |
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title | I2C Address for RTC |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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CAN Transceiver
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anchor | Table_OBP_CAN |
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title | CAN Tranciever interface MIOs |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Functionality | Connection Between | Notes |
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J6 | HD_GPIO_15 | Level Translator U3 and U5 | If you install the jumper HD_GPIO_15 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3). | J7 | HD_GPIO_11 | Level Translator U3 and U5 | If you put the jumper HD_GPIO_11 will be driven through Level Translator (U5) and Grove (J5) otherwise it goes to Level Translator (U3). | J10 | Voltage select | 5 V, 3.3 V | Pull up Voltage |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
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anchor | Table_PWR_PCOBP |
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title | Power ConsumptionOn board peripherals |
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orientation | portrait |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Chip/Interface | Designator | Notes |
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-- | -- | -- |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power is supplied by Ultra96 Board through SMD Header J3.
Power Consumption
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anchor | FigureTable_PWR_PSPC |
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title | Power SequencyConsumption |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Power Input Pin | Typical Current |
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5V | TBD | VCC_PSAUX | TBD |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | TableFigure_PWR_PRPD |
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title | Module power rails.Power Distribution |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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diagramName | TEP0006_PWR_PD |
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Power-On Sequence
There is no specific power on sequence, after power on the Ultra96 Board all electrical components on TEP0006 will be enabled.
Power Rails
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anchor | Table_PWR_BVPR |
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title | Zynq SoC bank voltagesModule power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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| Schematic Name | | Notes |
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...
...
use "include page" macro and link to the general B2B connector page of the module series,
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Power Rail Name | LS Expansion Connector Pin | Direction | Notes |
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+5V | 37 | Input | Supplied by Ultra96 | VCC_PSAUX | 35 | Input | Supplied by Ultra96 |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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Symbols | Description | Min | Max | Unit |
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V | |
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T_STG | Storage Temperature | -55 | 150 | °C |
V | V | V | V | V | V | V
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Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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Parameter | Min | Max | Units | Reference Document |
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V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | Parameter | Min | Max | Units | Reference Document |
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T_OPT | -40 | +85 | °C |
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Physical Dimensions
Module size: ?? 85 mm × ?? 17 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? 1.6 mm.
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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border | false |
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revision | 3 |
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diagramName | TEP0006_TS_PD |
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title | Physical Dimension |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixedImage Added |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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Date | Revision | Changes | Documentation Link | | Revision | Changes | Documentation Link |
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2019-07-19 | 01 | Initial Release | REV01 | - |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
scroll-title |
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| Board hardware revision number. |
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fitWindow | false |
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revision | 4 |
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diagramName | TEP0006_RV_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 180 |
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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anchor | Table_RH_DCH |
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title | Document change history. |
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cellHighlighting | true |
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Date | Revision | Contributor | Description| |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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