TE0300 is provided with a slide switch S3.
Slide switch S3 conditions the value of signal PS_EN.
In this way, S3 conditionally/unconditionally enables the power rails 1.2 V and 2.5 V.
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Note. DNP: Do Not Populate aka Do Not Solder the Component associated to DNP label. |
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control.When S3 is turned on (closed, FX2 PON), the power rails 1.2 V and 2.5 V are controlled by the USB (EZ-USB FX2LP USB FX2) microcontroller. At start-up, the USB microcontroller switches off the power rails 1.2 V and 2.5 V and starts up the module in low-power mode. After enumeration, the USB microcontroller firmware enables (switches on) the power rails 1.2 V and 2.5 V, if enough current is available from the USB bus.
When S3 is turned off (open, PON), the power rails 1.2 V and 2.5 V are always enabled (switched on).
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When S3 is turned on (FX2 PON), make sure that no signals are applied to the input pins when power-rails are disabled by the USB microcontroller (at start-up). |
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To command signal FX2_PS_EN, read the reference firmware code.
IOD = 0x03; // Enable PS_EN and disable PROG_B
OED = 0x03; // Configure PS_EN and PROG as outputs
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Table from EZ-USB(R) Technical Reference Manual (EZ-USB_TRM.pdf). |
Signal PS_EN enables (1) or disables (0) power rails 1.2 V and 2.5 V.
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Power-rail 3.3V is not controlled by signal PS_EN and is unconditionally enabled.
Figure 37: Power rail 3.3V could not be enabled/disabled by signal PS_EN.
The power-rail 3.3 V though is out of the control of the USB-microcontroller and is supplied down-converting the power supply 5 V provided by either the USB-bus or the B2B receptacle connector. In this case, signals that are applied to the 3.3 V I/O banks do not need to be disconnected when power-rails are disabled by the USB microcontroller.
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According to the corresponding assembly option, power rail VCCCIO0 can depend or not on the power rail 2.5V.
Voltage VccIO for bank B0 shall span from 1.2 V to 3.3 V. VccIO can be supplied either externally or internally to the micromodule.
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Warning! Spartan-3 I/Os are not 5 V tolerant. Applying more than the recommended operating voltages at any pin, results in a damaged FPGA (see Xilinx Answer AR#19146). |
VccIO can be externally supplied over the B2B connector J4. If bank B0 is not used, then VccIO can be left open.
If VccIO is not externally supplied, it can be internally supplied by one of the internal power rails of 2.5 V and 3.3 V. This is possible by short-circuiting one of the two pad pairs placed on the right of connector J4 at the top right corner of the bottom side of the micromodule.
Two suitable ways of shirt-circuiting the paid pair are by means of a zero-ohm 0603 (1608 metric) chip resistor or a solder blob.
Figure 37: example of VCCIO0 assembly.
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When slide switch S3 is in the left position ( = FX2 PON : power rails conditionally on depending on signal FX2_PS_EN), signal PS_EN is set to signal FX2_PS_EN (PS_EN = FX2_PS_EN) driven by the EZ-USB FX2LP USB FX2 microcontroller under user control (IOD and OED of fw.c).
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VCCCIO0 (2.5V) FPGA bank 0 (if R102+R103- assembly)
Full power operation (PS_EN = 1): when slide switch S3 is in the right position (PON = power rails unconditionally on), signal PS_EN is set to power rail 3.3V. Thus power rails 1.2 V and 2.5 V are unconditionally enabled.
Figure 39:
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Summary table
Table 14 The table below summarizes all switching options implied by slide switch S3 and firmware signal FX2_PS_EN (under the standard assembly option).
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(1) R102 populated / R103 unpopulated (2) R102 unpopulated / R103 populated |
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Table 40: Slide switch S3 settings overview ( 1.2V , 2.5V, VCCIO0).
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