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Overview

CPLD Device with designator U5: LCMX02-1200HC.

Feature Summary

• JTAG
• UART
• I2C
• Power
• Boot Mode
• Reset
• SD
• LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

Dip Switch

JTAG

JTAG signals routed directly through the CPLD to module in B2B connector.

TEB2000 CPLD can be selected with JTAGEN (DIP -switch S2-3). Access between CPLD of the TEB2000 board and the plugged module same as TEM0007 can be multiplexed via JTAGEN (S2-3).  Logical one is for accessing to CPLD of TEB2000 (OFF) and  logical zero is for the module (ON).

Access to FPGA of the plugged module or its CPLD  can be switched with PROGMODE which is driven by CM0 (DIP switch S2-2). CM1 and CM0 are pulled up in CPLD internally.

EN1

EN1 is set to one in firmware permanently.

NOSEQ

NOSEQ pulled up to 3.3V. NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is already prepared for the i2c interface in linux. 

i2cset -y <related bus> 0x20 0x02 0x00

It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x00

i2cset -y <related bus> 0x20 0x02 0x01

It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x01

To read the NOSEQ status, GPIO_input[16] must be read like the following instruction: 

i2cget -y <related bus> 0x20 0x02

For example --> i2cget -y 0 0x20 0x02

Note that the bus number depends on the linux design and can be varied for different designs.

PGOOD

PGOOD pulled up to 3.3V in CPLD internally. PGOOD pin can be set or reset by user. If CM1 set to high (S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.

MODE

This pin can be controlled with dip switch S2-4 (MIO0).

Reset

There is two reset switchs on the board (S1 and S6). The S6 is a soft reset button (SRST) that is not directed to CPLD chip. The S1 signal is connected to CPLD chip and is used in firmware code to create a reset signal. RESIN signal is the output reset signal of the CPLD and  is driven by S1 (Push Button). Button push button. The S1 push button is debounced.

Boot Mode

UART 

MIO14 is driven by BDBUS0 (FTDI RX). BDBUS1 (FTDI TX) is driven by MIO15 . MIO13 is driven by UART_TXD. UART_RXD is driven by MIO12.

SD

SD

For plugged polarfire SoC module same as TEM0007 the boot mode can not be selected via MODE and PGOOD pins, because polarfire SoC boot mode can be selected  only via HSS design for TEM0007.

UART 

MIO14 is driven by BDBUS0 (FTDI RX). BDBUS1 (FTDI TX) is driven by MIO15 . MIO13 is driven by UART_TXD. UART_RXD is driven by MIO12.

SD

SD selection (SD_SEL) is set to GND (SD Card slot). MIO9 is switched to SD_CD (Card Detect) and its status depends on SD_CD .

On-board LEDs

In Linux console enter: i2cset -y 0 0x20 0x02 0x00 and S2-4 = ON*

In Linux console enter: i2cset -y 0 0x20 0x02 0x00 and S2-4 = OFF*

In Linux console enter: i2cset -y 0 0x20 0x02 0x01 and S2-4 = ON*

In Linux console enter: i2cset -y 0 0x20 0x02 0x01 and S2-4 = OFF*

^{*Note: The related bus number of I2C can be varied and it depends on the Linux design. For example the bus number is 0 here.}

I2C to GPIO

I2C to GPIO is a subsystem in firmware of CPLD that provides an i2c interface that writes received data to GPIO_output 8 bit registers or reads  8 bit GPIO_input registers and send read data to i2c bus. 

I2C bus is connected to MIO10 ( SCL signal) and MIO11 (SDA signal). MIO10 to MIO15 are direct connection between CPLD of TEB2000 and FPGA on the module (for example TEM0007) through B2B connector. If in FPGA design exists  no i2c interface for MIO10 and MIO11, this block will be unused. More information about MIO10 to MIO15 are shown in the following table for TEM0007 modules and TEB2000 carrier board:

I2C to GPIO registers access methods

I2C to GPIO subsystem has 4 output and 4 input 8 bit registers. These registers can be written or read in linux  as shown in the following tables:

i2cget -y 0 0x20 0x00

i2cget -y 0 0x20 0x01

i2cget -y 0 0x20 0x02

i2cget -y 0 0x20 0x03

i2cset -y 0 0x20 0x00 <8bit data>

i2cset -y 0 0x20 0x01 <8bit data>

i2cset -y 0 0x20 0x02 <8bit data>

i2cset -y 0 0x20 0x03 <8bit data>

^{*The related bus number can be varied with Linux design. For example the bus number is 0 here.}

Note that resetting due to SRST push button or rebooting via reboot command in linux console will not delete the saved changed status of GPIO_output registers via i2c interface. However, resetting with the S1 reset button deletes all saved data in GPIO_output registers and sets these registers to the default values. 

I2C to GPIO registers

GPIO input registers

The following port or signals can be read via GPIO_input[ ] registers. 

^*Note: CPLD_REVISION[7:0] = Firmware version

GPIO output registers

 The following port or signals can be written via GPIO_output[ ] registers.

Appx. A: Change History and Legal Notices

Revision Changes

• Changes REV01 to REV02

  • Bug fix: The process of GPIO_output read/write needed a reset signal to avoid i2c error by i2c reading or i2c writing first time after switching on. 

  • The changed data in GPIO_output register will be reset to default value by resetting via S1 bush button. But rebooting via reboot command in linux or resetting via SRST button switch will not reset the GPIO_output register. 

  • Unnecessary signal same as CR5 and CR4 has been deleted.  

  • Internal oscillator frequency of CPLD is increased from 12.09MHz to 24.18MHz.

  • GPIO_input[30] is allocated to MIO0 (MODE) instead of S1.

  • GPIO_output register mapping changed. 

  • FLED_1 and FLED_2 function changed.

•  REV01

  • I2C port added.

  • I2C to GPIO component added.

  • NOSEQ can be changed via I2C port.

  • I2C port added.

  • I2C to GPIO component added.

  • NOSEQ can be changed via I2C port.

  • UART1 port added. This board has two UART ports. (UART0 and UART1)

  • New construction for UART0 and UART1 serial interfaces

  • Generic parameter CPLD_REVISION added.

  • JTAG timing correction

  • LED states and related ports/signals are changed. --> SD_CD, NOSEQ, MIO0, PGOOD, CM0 and CM1

  • New mapping for related ports/signals to GPIO_input and GPIO_output registers

  • New Ports are defined according to the schematic or revision 1

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Appx. B: Legal Notices