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Connector J4 has not been changed.

LED0

With TE0300-00, the LED is lit when the U_LED line on pin T15 is set high whereas with TE0300-01 the LED is lit when the U_LED line on pin R10 is set high.

Volatile Memory Interface

TE0300-00 could access the DDR SDRAM only with Xilinx OPB (on-chip peripheral bus) cores.
TE0300-01 can also access the DDR SDRAM through the dedicated Xilinx MIG (memory interface generator) memory interface.