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Refer to http://trenz.org/teg2000-info for the current online version of this manual and other available documentation.
This page describes briefly how to generate the fpga configuration file (Bitstream/cfg file) from one of the provided test projects the blink-example and how to program the FPGA. For a more detailed description of the tools follow the Quick start section of colognechip ug1002.
Key Features
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Design supports following modules:
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*used as reference |
Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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Design Sources
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*used as reference |
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Prebuilt
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Notes :
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| Design sources
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Toolchain | <project folder>\bin | script-based tools for synthesis, implementation, bitfile generation and programming | ||||||||||||||||||||||||||||||||||||||
fpga project | <project folder>\workspace\blink\log <project folder>\workspace\blink\net <project folder>\workspace\blink\sim <project folder>\workspace\blink\src | .bat scripts can be used for synthesis & implementation & programming |
Additional Sources
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title | Additional design sources |
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Prebuilt
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| File with description to generate Bin-File | |||||||||||||||||||||||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | ||||||||||||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File | ||||||||||||||||||||||
Boot Script-File | *.scr | Distro Boot Script file | ||||||||||||||||||||||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | ||||||||||||||||||||||
Debian SD-Image | *.img | Debian Image for SD-Card | ||||||||||||||||||||||
Diverse Reports | --- | Report files in different formats | ||||||||||||||||||||||
Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | ||||||||||||||||||||||
Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | ||||||||||||||||||||||
LabTools Project-File | *.lpr | Vivado Labtools Project File | ||||||||||||||||||||||
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | ||||||||||||||||||||||
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | ||||||||||||||||||||||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | ||||||||||||||||||||||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | ||||||||||||||||||||||
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems | ||||||||||||||||||||||
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sortDirection | ASC | |||||||||||||||||||||||
repeatTableHeaders | default | style | widths | |||||||||||||||||||||
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File | File-Extension | Description | ||||||||||||||||||||||
Constraint-File | *.ccf | FPGA pin constraint for pin-location, naming, input-output setting etc. | ||||||||||||||||||||||
Design source-files | *.v *.vhd | hdl design files describing the fpga functional description and I/O signals | ||||||||||||||||||||||
Config File | *.cfg | Config File Data for FPGA. Comments included. | ||||||||||||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File |
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Download
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Reference Design is available on:
It contains the tools, the example project blink and several other sample projects(those are not documented here).
Design Flow & Launch
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- After downloading the test design go into the directory <project folder>\workspace\blink\
- On Windows you can now run the *.bat scripts.
- Run synth.bat
- Run impl.bat
- Connect the Board (TEG2000 + TE0703 carrier) to power and USB, see Getting started.
- Run flash.bat to program the on-board qspi flash
- Press reset, the green LED D2 should be blinking
System Design
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Reference Design is available on:
Design Flow
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It's recommended to use TE prebuilt files for first launch. |
→ HOW TO OPEN PROJECT and PROGRAM ←
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Get prebuilt boot binaries
QSPI-Boot mode
JTAG
Not used on this example.
Usage
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HDL Sources
The design source files exist in verilog and in vhdl.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blink is
port (
clk : in std_logic;
rst : in std_logic;
led : out std_logic
);
end entity;
architecture rtl of blink is
component CC_PLL is
generic (
REF_CLK : string; -- reference input in MHz
OUT_CLK : string; -- pll output frequency in MHz
PERF_MD : string; -- LOWPOWER, ECONOMY, SPEED
LOW_JITTER : integer; -- 0: disable, 1: enable low jitter mode
CI_FILTER_CONST : integer; -- optional CI filter constant
CP_FILTER_CONST : integer -- optional CP filter constant
);
port (
CLK_REF : in std_logic;
USR_CLK_REF : in std_logic;
CLK_FEEDBACK : in std_logic;
USR_LOCKED_STDY_RST : in std_logic;
USR_PLL_LOCKED_STDY : out std_logic;
USR_PLL_LOCKED : out std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK_REF_OUT : out std_logic
);
end component;
signal clk0 : std_logic;
signal counter : unsigned(26 downto 0);
begin
socket_pll : CC_PLL
generic map (
REF_CLK => "10.0",
OUT_CLK => "100.0",
PERF_MD => "ECONOMY",
LOW_JITTER => 1,
CI_FILTER_CONST => 2,
CP_FILTER_CONST => 4
)
port map (
CLK_REF => clk,
USR_CLK_REF => '0',
CLK_FEEDBACK => '0',
USR_LOCKED_STDY_RST => '0',
USR_PLL_LOCKED_STDY => open,
USR_PLL_LOCKED => open,
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK_REF_OUT => open
);
process(clk0)
begin
if rising_edge(clk0) then
if rst = '0' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;
led <= counter(26);
end architecture;
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Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Power On PCB
title | boot process |
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System Design - Vivado
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Note: Description of Block Design, Constrains... BD Pictures from Export... |
Constraints
Basic module constraints
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## blink.ccf # # Date: 2022-10-21 # # Format: # <pin-direction> "<pin-name>" Loc = "<pin-location>" | <opt.-constraints>; # # Additional constraints can be appended using the pipe symbol. # Files are read line by line. Text after the hash symbol is ignored. # # Available pin directions: # # Pin_in # defines an input pin # Pin_out # defines an output pin # Pin_inout # defines a bidirectional pin # # Available pin constraints: # # SCHMITT_TRIGGER={true,false} # enables or disables schmitt trigger (hysteresis) option # PULLUP={true,false} # enables or disables I/O pullup resistor of nominal 50kOhm # PULLDOWN={true,false} # enables or disables I/O pulldown resistor of nominal 50kOhm # KEEPER={true,false} # enables or disables I/O keeper option # SLEW={slow,fast} # sets slew rate to slow or fast # DRIVE={3,6,9,12} # sets output drive strength to 3mA..12mA # DELAY_OBF={0..15} # adds an additional delay of n * nominal 50ps to output signal # DELAY_IBF={0..15} # adds an additional delay of n * nominal 50ps to input signal # FF_IBF={true,false} # enables or disables placing of FF in input buffer, if possible signal # FF_OBFIBF={true,false} # enables or disables placing of FF in outputinput buffer, if possible # LVDSFF_BOOSTOBF={true,false} # enables increasedor LVDSdisables output current of 6.4mA (default: 3.2mA) # LVDS_TERM={true,false} # enables on-chip LVDS termination resistor of nominal 100Ohm,placing of FF in output buffer, modeif onlypossible # LVDS_BOOST={true,false} # Global IOenables constraintsincreased canLVDS beoutput setcurrent withof the6.4mA (default_GPIO: statement. It can be # overwritten by individual settings for specific GPIOs, e.g.:3.2mA) # LVDS_TERM={true,false} # default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten # Pin_in "clk" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; Pin_out "UART_TXD" Loc = "IO_SB_A4"; # MIO15 Pin_out "led" Loc = "IO_SB_B4"; # one board LED #Pinenables on-chip LVDS termination resistor of nominal 100Ohm, in output mode only # # Global IO constraints can be set with the default_GPIO statement. It can be # overwritten by individual settings for specific GPIOs, e.g.: # default_GPIO | DRIVE=3; # sets all output strengths to 3mA, unless overwritten # Pin_in "resetnclk" Loc = "IO_EASB_B2A8"; # TEB0707 user button active high! #Pin| SCHMITT_TRIGGER=true; Pin_in "resetnrst" Loc = "IO_SBEB_B6B0"; # permanent 1SW3 #PinPin_in out "resetnled" Loc = "IO_SB_B5B4"; # permanent 0 D1 |
Additional Software
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No additional software is needed.
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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Legal Notices
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