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Note
Currently only for Intel SoC / FPGA with external DDR

The Yocto Project is a set of tools that helps to create customized Linux systems. This is a short description of how to prepare the host computer and how to create a project with yocto.

Used source files

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The following description was tested with the source files listed in this table:

Component	Source	Version/Git branch	Commit ID
Oracle VM VirtualBox	https://www.virtualbox.org/	6.1.26	---
Ubuntu 20.04 LTS	https://releases.ubuntu.com/20.04/	20.04.3 LTS	---
Yocto	https://git.yoctoproject.org/cgit/cgit.cgi/poky/	dunfell	b47125666fe44e491ce9a4ecadd1875bec9891db
meta-altera	https://github.com/kraj/meta-altera.git	dunfell	237cd5ecd28491dbcff16d8d64662d3b56ac30df
linux -socfpga	https://github.com/altera-opensource/linux-socfpga.git	socfpga-5.4.124-lts	cdb318393975f4bf9a392fb15af74aad45c57245
u-boot-socfpga	https://github.com/altera-opensource/u-boot-socfpga.git	socfpga_v2021.04	bdc9a4409de9cef4408eebd81196fd63887ac78f

Build Host

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Yocto Project is supported in many Linux Distributions, this descriptions refers to Ubuntu 20.04 LTS. Information and requirements for other distributions can be found in the Yocto Project Reference Manual.

General requirements

This requirements are generally needed for Yocto Project in Ubuntu 20.04:

free disk space: at least 50 GB

required packages:

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sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath socat cpio \
                 python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 \
                 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev

(optional) VM with supported Linux OS

If you do not have installed Linux OS on your host computer, you can optionally run a VM with a supported Linux OS:

- e.g. with OracleVM:
  - VM Setup:
    - RAM: >= 8 GB
    - CPU: >= 4
    - HDD: 200 GB dynamically
      - ubuntu-20.04-desktop-amd64.iso
      - install vm guest additions
    - Network: network bridge
    - optional: add shared folder, enable drag and drop
  - Note the general requirements

Install Yocto Project

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Create and navigate to the yocto directory:
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mkdir yocto && cd yocto
Clone the Yocto Project sources:
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git clone -b dunfell https://git.yoctoproject.org/git/poky

Create a project for an Intel SoC/FPGA device

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The following steps are required to create an image for the Intel SoC/FPGA devices:

For Intel SoC/FPGA devices you need the meta-layer 'meta-altera'. Run following command to clone this meta-layer from github into the 'poky' folder:
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cd poky git clone -b dunfell https://github.com/kraj/meta-altera.git
Run the oe-init-build-env script to initialize the environment:
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source oe-init-build-env
Add meta-altera layer to path/to/yocto/poky/build/conf/bblayers.conf:
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bitbake-layers add-layer ../meta-altera
Modify the path/to/yocto/poky/build/conf/local.conf file:
1. Remove default configuration of the MACHINE variable and set it to a supported machine (see meta-altera/conf/machine for more information) of meta-altera layer e.g 'cyclone5':
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  sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf echo -e '\nMACHINE = "cyclone5"' >> conf/local.conf
2. Set the preferred linux kernel version (see meta-altera/recipes-kernel/linux for other linux kernel versions):
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  echo -e '\nPREFERRED_PROVIDER_virtual/kernel = "linux-altera-lts"' >> conf/local.conf echo -e 'PREFERRED_VERSION_linux-altera-lts = "5.4%"' >> conf/local.conf
3. Set the preferred u-boot version (see meta-altera/recipes-bsp/u-boot for other u-boot versions):
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  echo -e '\nPREFERRED_VERSION_u-boot-socfpga = "v2021.04%"' >> conf/local.conf
Build the image:
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bitbake core-image-minimal
The first run of this command can take several hours.
The generated files such as the u-boot file, kernel file or the complete Image (.wic file) are stored in /yocto/poky/build/tmp/deploy/images/<MACHINE>/.
Follow the steps described in Reference Designs with Yocto - Intel SoC FPGAs#Copy .wic file to SD card to copy the .wic file to the SD card.

References

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Overview

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Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

NIOS II Design with SDRAM Controller and 4 different LED sequences, that can be toggled using the user button.

Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.

Key Features

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Add basic key futures, which can be tested with the design

Excerpt
Quartus 18.1 NIOS II SPI UART ADC User Flash memory SDRAM memory User LEDs User buttons

Revision History

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add every update file on the download
add design changes on description

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initial release

Release Notes and Know Issues

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add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

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Requirements

Software

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list of software which was used to generate the design

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Hardware

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list of software which was used to generate the design

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Download

Reference Design is only usable with the specified Quartus version. Do never use different Versions of Quartus Software for the same Project.

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Important set new Quartus version link on every Design update of new quartus version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TEI0015 "Test Board" Reference Design

Design Flow

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Basic Design Steps
Add/ Remove project specific description

Open file "test_board.quar"
Select Tools → Platform Designer from Quartus menu
Open file "NIOS_test_board.qsys" in Platform Designer
Open the component "onchip_flash" (double-click)
1. Enable "Initialize flash content" and "Enable non-default initialization file" at Flash Initialization, if disabled
2. Specify Path for "User created hex or mif file". You can find the file at \software\test_board\mem_init\onchip_flash.hex
Select Generate → Generate HDL... from the Platform Designer menu
The Generation window will appear
1. Select "VHDL" as the synthesis language and "None" from the simulation model dropdown menu
2. Select “Create block symbol file(.bsf)”, if not selected
3. Click Generate and close Platform Designer
Select Processing → Start Compilation from the Quartus menu to compile the Design

Launch

Programming

MAX10 Flash

Connect the Board to USB-Port
Open Quartus Programmer from Tools → Programmer
If the Arrow-USB-Blaster is not visible:
1. Click "Hardware Setup..."
2. Choose at the drop-down menu "Currently selected hardware" the Arrow-USB-Blaster[USB0]
3. Close "Hardware Setup"
If the correct configuration file is not set:
1. Delete other files
2. Click "Add file..."
3. select the correct *.pof file (Path: <project_directory>\output_files\test_board.pof)
Click start

Usage

Prepare Hardware like described on section TEI0015 Test Board
Connect UART USB (most cases same as JTAG)

UART

Open Serial Console "PuTTY"
Change settings in category "Session"
1. Connection Type: Serial
2. COM Port: see device manager (Win OS)
3. Speed: 115200
Select "Implicit CR in every LF" in category "Terminal"
Click Open
Press reset button at module
1. Flash test is running
After the flash test finished, you can toggle between following LED sequences by pressing user button
1. Case statement sequence
2. Shift register sequence
3. Knightrider sequence
4. Pulse-width modulation sequence

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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It's semi automatically, so do following
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- Metadata is only used of compatibility of older exports

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Initial release

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Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 3

New Version Current

Key

Used source files

Build Host

General requirements

(optional) VM with supported Linux OS

Install Yocto Project

Create a project for an Intel SoC/FPGA device

References

Table of contents

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Download

Design Flow

Launch

Programming

MAX10 Flash

Usage

UART

Appx. A: Change History and Legal Notices

Document Change History

Legal Notices