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The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 a Intel MAX 10 FPGA SoC, 2 8 MByte serial memory for configuration and operationuser application, 8 MByte SDRAM and a 3-axis accelerometer.

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Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.

Key Features

Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC
8 MByte SDRAM
2 8 MByte serial configuration QSPI Flash memory
ST Microelectronics LIS3DH 3-axis accelerometer
JTAG and UART over Micro USB2 connector
1x6 pin header for JTAG access to FPGA SoC
1x PMOD header providing 8 GPIOs
2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs22 GPIOs with 7 analog inputs as alternative function
1x 3-pin header providing 2 GPIOsanalog inputs or 1 GPIO
8x user LEDs
1x user push button
5.0V single power supply with on-board voltage regulators
Size: 61.5 x 25 mm

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Main Components

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Intel MAX 10 10M08 FPGA SoC, U1
Intel Cyclone 10LP 10CL025 FPGA SoC, U1
Winbond W9864G6JT 8 Mbyte SDRAM 166MHz, U2
Intel EPCQ16ASI8N 2 MByte serial configuration memory8 Mbyte QSPI Flash memory, U5
ST Microelectronics LIS3DH 3-axis accelerometer, U4
FTDI USB2 to JTAG/UART adapter, U3
Configuration EEPROM for FTDI chip, U9
12.0000 MHz oscillator, U7
8x red user LEDs, D2 ... D9
Red LED (Conf. DONE), D10
Green LED (indicating supply voltage), D1
Push button (user), S2
Push button (reset), S1
Micro USB2 B socket (receptacle), J9
1x14 pin header (2.54mm pitch), J2
1x6 pin header (2.54mm pitch), J4
2x6 Pmod connector, J6
3-pin header (2.54mm pitch), J3
1x14 pin header (2.54mm pitch), J1

Initial Delivery State

Storage device name	Content	Notes

Serial configuration memory

Quad SPI Flash, U5	DEMO Design	-
I²C Configuration EEPROM, U9	Programmed	-

Table 1: Initial delivery state of programmable devices on the module

Boot Process

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power offBy default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.

Signals, Interfaces and Pins

...

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

Bank	Connector Designator	I/O Signal Count	Bank Voltage	Notes
2

J2

J1

9

4 I/O's	3.3V	-
J6	3.3V

2

8 I/O's

of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I

	Pmod connector
5	J1	2 I/O's

of same bank or pins can be shared4J1

	3.3V	-
J2	3.3V	9

8

I/O's

3.3V-J3

2 I/O's

of bank 5 can be pulled-up to 3.3V

-5

(4K7 resistors)
1A	J1

6 I/O's

7x analog inputs or GPIO's, 1x Analog reference voltage (AREF)

3.3V

-6J68 I/O's3.3VPmod Connector1J4

analog pins usable as GPIO's as alternative function
analog pins usable as GPIO's as alternative function	J3	1x analog inputs or GPIO, 1x dedicated analog input
1B	J4	JTAG interface and 'JTAGEN' signal (5

4

I/O's)

3.3V

JTAG

interfaceJ21 Input3.3Vlow active Reset input

enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

Bank

VCCIO

	I/O's Count	Connected to	Notes

1

2

3.3V6LIS3DH digital motion sensor, U4SPI interface, 2 interrupt lines41x6

4	1x14 pin header,

J4JTAG interface42 MByte serial configuration memory, U5FPGA configuration memory with active serial (AS) x1 interface1J2-10, push button S1 low active reset input2

J1	user GPIO's
8	Pmod connector, J6	user GPIO's
1	clock oscillator, U7	12.0000 MHz reference clock input
1	optional clock oscillator, U6	oscillator not fitted, footprints available for Microchip MEMS oscillator
5

3.3V

9

1x14 pin header, J2

GPIOs (

2 I/O's (D11, D12) of bank

2

5 can be pulled-up to 3.3V (4K7 resistors) with

2

1 I/O

's

(D12_R) of same Bank

or pins can be shared)33.3V8LEDs D2 ... D98 x red user LEDs8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces1push button S2user button43.3V10pin headers J1, J3GPIOs53.3V6pin headers J1GPIOs63.3V8Pmod connector J6GPIOs

and 1 I/O (D11_R) of bank 6
6	18	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
3	22	8 MByte SDRAM 166MHz, U2	16bit SDRAM memory interface
3	6	LIS3DH 3-axis accelerometer, U4	4 I/O's for SPI interface, 2 interrupt lines
1A	8	1x14 pin headers J1	7 analog inputs or GPIO's, 1 pin analog reference voltage input
1A	2	pin headers J1	1 analog inputs or GPIO, 1 dedicated analog input
1B	5	pin header J4	4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
8	8	LEDs D2 ... D9	Red user LEDs
	6	QSPI Flash memory, U5	6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
	6	FTDI FT2232H JTAG/UART Adapter, U3	6 pins configurable as GPIO/UART or other serial interfaces
	1	Red LED, D10	Configuration

1Red LED, D10Configuration

DONE Led (ON when configuration in progress, OFF when configuration is done)

73.3V198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface83.3V218 Mbyte SDRAM 166MHz, U2

1	User button S2	user configurable
1	Reset button S1 and pin J2-10	low active reset line for FPGA reconfiguration

16bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

JTAG Signal	Pin on Header J4	Note
TCK	3	-
TDI	5	-
TDO	4	-
TMS	6	-
JTAGEN	2	leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs

Table 4: optional JTAG pin header

...

On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N Winbond W74M64FVSSIQ with 16 64 MBit (2 8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 SPI interface.

Serial Memory U5 Pin	Signal Schematic Name	Connected to	Notes
Pin

2

1,

DATA1

CS

AS

F_

DATA0

CS

FPGA bank

1

8, pin

H2

B3

Data out

chip select

5

6,

DATA0

CLK

AS

F_

ASDO

CLK

FPGA bank

1

8, pin

C1

A3

Data in

clock

1

5,

nCS

SI/IO0

AS

F_

NCS

DI

FPGA bank

1

8, pin

D2

A2	data in / out

chip select

6

7,

DCLKAS_DCLK

HOLD/IO3

NSTATUS

FPGA bank

1

8, pin

H1clock

Table 5: Serial configuration memory interface connections

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 7 and 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

C4	data in / out, configuration dual-purpose pin of FPGA
Pin 3, WP/IO2	DEVCLRN	FPGA bank 8, pin B9	data in / out, configuration dual-purpose pin of FPGA
Pin 2, SO/IO1	F_DO	FPGA bank 8, pin B2	data in / out

Table 5: Quad SPI Flash memory interface

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I

SDRAM I

/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank

8

3	-
Bank address inputs	BA0 / BA1	bank

8

3	-
Data input/output	DQ0 ... DQ15	bank

7

6	-
Data mask	DQM0 ... DQM1	bank

7

6	-
Clock	CLK	bank

7

3
Control Signals	CS	bank

8

3	Chip select
CKE	bank

8

3	Clock enable
RAS	bank

8

3	Row Address Strobe
CAS	bank

8

3	Column Address Strobe
WE	bank

8

3	Write Enable

Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 .0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of channel A and 6 I/O's of Channel B are routed to FPGA bank 3 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
Pin 12, ADBUS0	TCK	FPGA bank

1, pin H3

1B, pin G2	JTAG interface
Pin 13, ADBUS1		TDI	FPGA bank 1B, pin F5
Pin 14, ADBUS2		TDO	FPGA bank 1B, pin F6
Pin 15, ADBUS3		TMS	FPGA bank 1B, pin G1

JTAG interfacePin 13, ADBUS1TDIFPGA bank 1, pin H4Pin 14, ADBUS2TDOFPGA bank 1, pin J4Pin 15, ADBUS3TMS

FPGA bank 1, pin J5

Pin 17, ADBUS4ADBUS4FPGA bank 3, pin M8user configurablePin 20, ADBUS7ADBUS7FPGA bank 3, pin N8user configurable


Pin 32, BDBUS0	BDBUS0	FPGA bank

3

8, pin A4	user configurable
Pin 33, BDBUS1	BDBUS1	FPGA bank

3

8, pin B4	user configurable
Pin 34, BDBUS2	BDBUS2	FPGA bank

3

8, pin B5	user configurable
Pin 35, BDBUS3	BDBUS3	FPGA bank

3

8, pin A6	user configurable
Pin 37, BDBUS4	BDBUS4	FPGA bank

3

8, pin B6	user configurable
Pin 38, BDBUS5	BDBUS5	FPGA bank

3

8, pin A7

user configurable

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0003 TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Accelerometer U4 Pin	Signal Schematic Name	Connected to	Notes
Pin 11, INT1	SEN_INT1	FPGA bank

1

3, pin

B1

J5	Interrupt lines
Pin 9, INT2	Interrupt lines	SEN_INT2	FPGA bank

1

3, pin

C2

L4
Pin 6, SDA/SDI/SDO	SEN_SDI	FPGA bank

1

3, pin

G2

J7	SPI interface
Pin 7, SDO/SA0		SEN_SDO	FPGA bank

1

3, pin

G1

K5
Pin 4, SCL/SPC	SEN_SPC	FPGA bank

1

3, pin

F3

J6
Pin 8, CS	SEN_CS	FPGA bank

1

3, pin

D1

L5
Pin 13, ADC3	ADC3	5V	Sense 5V input voltage

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Clock Source	Schematic Name	Frequency	Clock Input Destination
Microchip MEMS Oscillator, U7	CLK12M	12.0000 MHz	FTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin

M2

H6
optional Microchip MEMS Oscillator, U6 (not fitted)	CLK_X	-	FPGA SoC bank

6

2, pin

E15

G5

Table 9: Clock sources overview

...

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

LED	Color	Signal Schematic Name	FPGA	Notes
D1	Green	-	-	Indicating 3.3V board supply voltage
D2	Red	'LED1'	bank

6

8,

pin M6

pin A8	user
D3	Red	'LED2'	bank

6

8,

pin T4

pin A9	user
D4	Red	'LED3'	bank

6

8, pin

T3

A11	user
D5	Red	'LED4'	bank

6

8, pin

R3

A10	user
D6	Red	'LED5'	bank

6

8,

pin T2

pin B10	user
D7	Red	'LED6'	bank

6

8, pin

R4

C9	user
D8	Red	'LED7'	bank

6

8,

pin N5

pin C10	user
D9	Red	'LED8'	bank

6

8,

pin N3

pin D8	user
D10	Red	'CONF_DONE'	bank

6

8, pin

H14

C5	indication configuration is DONE when LED is off

Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

Button	Signal Schematic Name	FPGA	Notes
S1	'USER_BTN'	bank

3

8, pin

N6

E6	user configurable
S2	'RESET'	bank

1

8, pin

H5

E7

system

FPGA reset

Table 11: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

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The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEI0003 TEI0001 module needs one single power supply of 5.0V nominal.

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border	false
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Power Consumption

FPGA	Design	Typical Power, 25C ambient
Intel

Cyclone 10LP 10CL025

MAX 10 10M08 FPGA SoC

Not configured

TBD*

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

...

There is no specific or special power-on sequence, just one single power source is needed.

Power Rails

Connector Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J2	5V	5.0V	Out	Pin 14	-
	VIN	5.0V	In	Pin 13	-
	3.3V	3.3V	Out	Pin 12	-
J6	3.3V	3.3V	Out	Pin 6, 12	-
J9	USB_VBUS	5.0V	In	Pin 1	-

Table 13: Connector power pin description

Bank Voltages

Bank	Voltage	Voltage Range

1

2

3.3V

all bank voltages fixed

23.3V


	3	3.3V

4

5

3.3V

5

6

3.3V

6

1A

3.3V

7

1B	3.3V
8	3.3V

Table 14: FPGA SoC VCCO bank voltages

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference document
VIN supply voltage (5.0V nominal)	-0.3	6.0	V	EP53A7HQI

/ EP53A7LQI

datasheet
I/O Input voltage for FPGA I/O bank	-0.5	4.

2

12

V

Intel

Cyclone

MAX 10

LP

datasheet
Storage Temperature	-40	+90	°C	LED R6C-AL1M2VY/3T datasheet

Table 15: Absolute maximum ratings

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference document
VIN supply voltage (5.0V nominal)	4.75	5.25	V	same as USB-VBUS specification
I/O Input voltage for FPGA I/O bank	–0.5	3.6	V	Intel

Cyclone

MAX 10

LP

datasheet
Operating temperature range	0	+70	°C	Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Note
Please check Intel Cyclone 10 LP datasheet for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions

...


Please check Intel MAX 10 datasheet for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions

Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.
PCB thickness: ca. 1.65mm
Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

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Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
-	03	Current available revision	-	TEI0001-03
-	02	First Production Release

-

TEI0003

TEI0001-02
-	01	Prototypes	-	TEI0001-01

Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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title	Figure 5: Module hardware revision number

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Document Change History

Date

Revision

Contributors

Description

Page info

modified-date

	modified-date
dateFormat	yyyy-MM-dd
	modified-date

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
type	Flat

Ali Naseri

small corrections

2018-06-29

v.17

Ali Naseri

First TRM release

Table 18: Document change history

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Trenz Electronic Documentation

Versions Compared

Old Version 3

New Version Current

Key

Key Features

Main Components

Initial Delivery State

Boot Process

Signals, Interfaces and Pins

FPGA I/O banks

JTAG Interface

SDRAM

SDRAM

FTDI FT2232H Chip

3-Axis Accelerometer

System Clock Oscillator

Push Buttons

Connectors

Power Consumption

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Disclaimer