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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/TEB0911+Master+CPLD

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Table of contents

Table of Contents
outlinetrue

Overview

Firmware for PCB-Master CPLD with designator U27.:LCMXO2-1200HC

Feature Summary

  • Power Management
  • Reset Management
  • FMC JTAG Management
  • FPGA Boot Mode
  • RGPIO Interface to FPGA

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name/ opt. VHD NameDirectionPinDescription
B64_T1          
 
out20
 
FPGA IO / Master RGPIO TX
B64_T2          
 
in19
 
FPGA IO / Master  RGPIO RX
B64_T3          
 
in21
 
FPGA IO / Master  RGPIO CLK
B65_T1          
 
out22FPGA IO  / Slave RGPIO TX
B65_T2          
 
in24
 
FPGA IO / Slave RGPIO RX
B65_T3          
 
in23
 
FPGA IO / Slave RGPIO CLK
C_TCK           
 
in131
 
JTAG
C_TDI           
 
in136
 
JTAG
C_TDO1          
 
out137
 
JTAG
C_TMS           
 
in130
 
JTAG
DDR
_EN          
_EN/EN_DDR         out
 
126
 
Power control
DDR_PG           121
 
Power control / currently_not_used
DONE            
 
in4
 
FPGA Control
DP_EN           
 
out34
 
Power control
EN_12V          
 
out114
 
Power control
EN_3.3V         
 
out112
 
Power control
EN_A_3V3        
 
out143
 
Power control
EN_AF_1V8       
 
out110
 
Power control
EN_B_3V3        
 
out74
 
Power control
EN_BC_1V8       
 
out84
 
Power control
EN_C_3V3        
 
out76
 
Power control
EN_D_3V3        
 
out78
 
Power control
EN_DE_1V8       
 
out77
 
Power control
EN_E_3V3        
 
out82
 
Power control
EN_F_3V3        
 
out104
 
Power control
EN_GT_L         
 
out122
 
Power control
EN_GT_R         
 
out125
 
Power control
EN_SFP          
 
out111
 
Power control
EN_SFP_SSD      
 
out3
 
Power control
EN_VCCINT       
 
out119
 
Power control
FAN_A_EN        
 
out106
 
Fan control
FAN_B_EN        
 
out83
 
Fan control
FAN_C_EN        
 
out81
 
Fan control
FAN_D_EN        
 
out75
 
Fan control
FAN_E_EN        
 
out73
 
Fan control
FAN_F_EN        
 
out109
 
Fan control
FMC12V
_EN       
_EN/EN_FMC_12Vout
 
95
 
Power control
FMC12V_PG        93Power control / currently_not_used
FMCA_PG_C2M      142Power control / currently_not_used 
FMCA_PG_M2C      141Power control / currently_not_used
FMCA_PRSNT      
 
in140
 
FMC
FMCA_TCK        
 
out139
 
FMC / JTAG
FMCA_TDI        
 
out138
 
FMC / JTAG
FMCA_TDO        
 
in133
 
FMC / JTAG
FMCA_TMS        
 
out132
 
FMC / JTAG
FMCB_PG_C2M      38
 
FMC / currently_not_used
FMCB_PG_M2C      39
 
FMC / currently_not_used
FMCB_PRSNT      
 
in40
 
FMC
FMCB_TCK        
 
out41
 
FMC / JTAG
FMCB_TDI        
 
out42
 
FMC / JTAG
FMCB_TDO        
 
in43
 
FMC / JTAG
FMCB_TMS        
 
out44
 
FMC / JTAG
FMCC_PG_C2M      54
 
FMC / currently_not_used
FMCC_PG_M2C      55
 
FMC / currently_not_used
FMCC_PRSNT      
 
in56
 
FMC
FMCC_TCK        
 
out57
 
FMC / JTAG
FMCC_TDI        
 
out58
 
FMC / JTAG
FMCC_TDO        
 
in59
 
FMC / JTAG
FMCC_TMS        
 
out60
 
FMC / JTAG
FMCD_PG_C2M      45
 
FMC / currently_not_used
FMCD_PG_M2C      47
 
FMC / currently_not_used
FMCD_PRSNT      
 
in61
 
FMC
FMCD_TCK        
 
out48
 
FMC / JTAG
FMCD_TDI        
 
out49
 
FMC / JTAG
FMCD_TDO        
 
in50
 
FMC / JTAG
FMCD_TMS        
 
out52
 
FMC / JTAG
FMCE_PG_C2M      62
 
FMC / currently_not_used
FMCE_PG_M2C      65
 
FMC / currently_not_used
FMCE_PRSNT      
 
in67
 
FMC
FMCE_TCK        
 
out68
 
FMC / JTAG
FMCE_TDI        
 
out69
 
FMC / JTAG
FMCE_TDO        
 
in70
 
FMC / JTAG
FMCE_TMS        
 
out71
 
FMC / JTAG
FMCF_PG_C2M      107
 
FMC / currently_not_used
FMCF_PG_M2C      105
 
FMC / currently_not_used
FMCF_PRSNT      
 
in100
 
FMC
FMCF_TCK        
 
out99
 
FMC / JTAG
FMCF_TDI        
 
out98
 
FMC / JTAG
FMCF_TDO        
 
in97
 
FMC / JTAG
FMCF_TMS        
 
out96
 
FMC / JTAG
INIT_B          
 
in5
FPGA Control
JTAGENB--120enable JTAG access to CPLD (one CPLD, zero FMC chain)
 
MIO24            1
 
FGPA MIO / currently_not_used
MIO25            2
 
FGPA MIO / currently_not_used
MODE0           
 
out10
 
FPGA Boot Mode
MODE1           
 
out12
 
FPGA Boot Mode
MODE2           
 
out9
 
FPGA Boot Mode
MODE3           
 
out11
 
FPGA Boot Mode
MR              
 
out92
 
FPGA Control
PG_12V          
 
in113
 
Power control
PG_FPD          
 
in115
 
Power control 
PG_GT_L         
 
in13
 
Power control
PG_GT_R         
 
in35
 
Power control
PG_PSGT         
 
in128
 
Power control
PROG_B          
 
out6
 
FPGA Control
PSGT_
EN         
EN/EN_GT_PS        out
 
117
 
Power control
SC_IO0          
 
out25
 
Slave CPLD / Reset
SC_IO1           26
 
Slave CPLD / currently_not_used
SC_IO2           27
 
Slave CPLD / currently_not_used
SC_IO3          
 
in28Slave CPLD / Slave RGPIO TX_IN 
SC_IO4          
 
out32
 
Slave CPLD / Slave RGPIO RX_OUT
SC_IO5          
 
out33
 
Slave CPLD / Slave RGPIO CLK_out
SC_SW1          
 
in127
 
DIP Switch S3-3
SC_SW2          
 
in85
 
DIP Switch S3-4
SC1_IO_SB        91Slave CPLD /  currently_not_used
SC2_IO_SB        86Slave CPLD /  currently_not_used
USR_BUT2        
 
in94
 
Button / Global Reset

 

Functional Description

JTAG

JTAGENB set CPLD into the Chain for Firmware update. In normal mode every FMC JTAG will be set into the chain, when his FMCx_PRSNT is detected.

Power

EN_12V and EN_VCCINT are enabled on power up. All other power enables will be set, if PG_12V and PG_FPD are valid.

Reset

PROG_B always one. MR and SC_IO0 controlled by USR_BUT2 (S2) and power management.

Bootmode

SD Boot, when SC_SW1 is one else SQPI Boot.

S4-3S4-5Description
OFFOFFSD1 Boot
OFFONPJTAG0
ONOFFQSPI32
ONONJTAG

 

FANs

6 FMC FANs controlled by corresponding FMCx_PRSNT signals to enable FANs only for active FMC slots.

RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

RGPIO Pin to FPGAValue
0-3current Boot Mode
4SC_SW1
5SC_SW2
6-7unused
8-13FMCA...F_PRSNT
14-19unused
20PG_PSGT
21PG_GT_L
22PG_GT_R
23unused
24-27reserved
28-31interface detection
RGPIO Pin from FPGAValue
0-23unused
24-27reserved
28-31interface detection

 

RGPIO slave is routed directly to Slave CPLD.

Appx. A: Change History

...

Revision Changes

CPLD REV04 to REV05

  • more Boot Modes selectable
  • Power startup sequence

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription
2016-04-11

 

REV01REV01

John Hartfiel

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2017-05-24v.26REV02REV01John HartfielRevision 02 finished
2016-10-16

v.22

REV01REV01

Oleksandr Kiyenko

Revision 01 finished
2016-04-11

 

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Appx. B: Legal Notices

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...