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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Table of contents

Table of Contents
outlinetrue

Overview

CPLD Device with designator U3: LCMX02-256HC

Feature Summary

  • Power Management
  • FPGA, USB Reset Managment
  • JTAG routing

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescription
3.3V / PG_SENSEin25Power Sense
DONE        in28FPGA Done Pin
EN1         in11Enable Pin From B2B
F_TCK       out17JTAG from/to FPGA
F_TDI       out23JTAG from/to FPGA
F_TDOin9JTAG from/to FPGA
F_TMS       out10JTAG from/to FPGA
FPGA_IO1 in21FPGA Pin
FPGA_IO2     20/ currently_not_used
FTDI_RESET_Nout5 USB FTDI Reset
JTAGEN      in26 Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)
MODE        in13/ currently_not_used
NOSEQ       inout14/ currently_not_used
PG_DDR_PWRin4 Power Good from DDR
PGOOD       out12Power Good to B2B
PROG_B      out27 FPGA PROG_B
RESIN       in16Reset Pin From B2B
SYSLED1out8LED (Green)
TCK    in30JTAG from/to B2B
TDIin32JTAG from/to B2B
TDO         out1JTAG from/to B2B
TMSin29JTAG from/to B2B

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Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).

Power

Power Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).

Reset

PROG_B is set to one, if power is good.

FTDI_RESET_N is set to one, if power is good.

LED

LEDDescription
SYSLED1 (Green LED D1)ON when RESIN=0, else FGPIO1 when DONE=1 else Blinking

Appx. A: Change History

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Revision Changes

Document Change History

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Appx. B: Legal Notices

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IN:Legal Notices
IN:Legal Notices

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