Page History
...
The 7 boot mode strapping pins (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).
The TE0722 -02 FPGA board is hardware programmed to boot initially from the on-board QSPI flash Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI flash Flash memory through the Zynq device.
Signals, Interfaces and Pins
...
| Bank | Type | Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
| 34 | HR | P1 | 8 | 3.3V | Signal Schematic names: 'P0' - 'P7' |
| 34 | HR | P2 | 8 | 3.3V | Signal Schematic names: 'P24' - 'P31' |
| 34 | HR | P2 | 10 single ended I/O's or 5 differential pairs | 3.3V | - |
| 34 | HR | J1 | 6 | 3.3V | Signal Schematic names: 'X2A' - 'X2F' |
| 34 | HR | J2 | 2 | 3.3V | - |
| 34 | HR | J3 | 4 | 3.3V | Signal Schematic names: 'X1A' - 'X1D' |
| 35 | HR | P1 | 8 single ended I/O's or 4 differential pairs | 3.3V | - |
Table 32: Zynq SoC PL I/O signals overview
Zynq SoC I/O Banks
| Bank | Type | VCCIO | I/O 's Signal Count | Available on Connectors | Notes |
|---|---|---|---|---|---|
| 34 | HR | 3.3V | 41 | 38 | 38 user I/O's, 3 I/O's used for controlling the RGB LED D4. |
| 35 | HR | 3.3V | 8 | 8 | 8 single ended or 4 differential. |
| 500 | PS MIO | 3.3V | 7 | 0- | 6 MIO - pins used for QSPI flash memory interface, 1 MIO - pin connected to green LED D2. |
| 501 | PS MIO | 3.3V | 10 | 0- | 7 MIO - pins used for SD Card interface, 3 MIO - pins connected to light sensor U4. |
| 0 | Config | 3.3V | 5 | 0- | 4 I/O's are dedicated to JTAG interface, 'DONE'-signal is indicated by red LED D6. |
Table 43: General overview of Zynq SoC PL/PS I/O banks
...
JTAG Signal | J2 Connector Pin |
|---|---|
| TCK | 4 |
| TDI | 9 |
| TDO | 10 |
| TMS | 8 |
Table 54: JTAG interface signals
Quad SPI Interface
...
| Zynq SoC's MIO-pin | U5 Pin | Signal Schematic Name |
|---|---|---|
| MIO1 | 1 | SPI0-CS |
| MIO2 | 5 | SPI0-DQ0/M0 |
| MIO3 | 2 | SPI0-DQ1/M1 |
| MIO4 | 3 | SPI0-DQ2/M2 |
| MIO5 | 7 | SPI0-DQ3/M3 |
| MIO6 | 6 | SPI0-SCK |
Table 65: Quad SPI interface signals and connections
...
| Zynq SoC's MIO-pin | J8 pin | Signal Schematic Name |
|---|---|---|
| MIO28 | J8-7 | DAT0 |
| MIO29 | J8-3 | CMD |
| MIO30 | J8-5 | CLK |
| MIO31 | J8-8 | DAT1 |
| MIO32 | J8-1 | DAT2 |
| MIO33 | J8-2 | CD/DAT3 |
| MIO49 | J8-G4 | Card detect switch |
Table 76: SD card interface signals
...
| Zynq SoC's MIO-pin | U4 pin | Signal Schematic Name |
|---|---|---|
| MIO36 | 2 | SCL |
| MIO37 | 1 | SDA |
Table 87: Zynq SoC I2C interface signals
...
| MIO-pin | Function | Connector to |
|---|---|---|
| MIO1 | QSPI | QSPI flash memory, pin 1 |
| MIO2 | QSPI | QSPI flash memory, pin 5 |
| MIO3 | QSPI | QSPI flash memory, pin 2 |
| MIO4 | QSPI | QSPI flash memory, pin 7 |
| MIO5 | QSPI | QSPI flash memory, pin 3 |
| MIO6 | QSPI | QSPI flash memory, pin 6 |
| MIO7 | GPIO | Green LED D2 |
| MIO28 | SDIO | SC SD Card socket. pin J8-5 |
| MIO29 | SDIO | SC SD Card socket. pin J8-3 |
| MIO30 | SDIO | SC SD Card socket. pin J8-7 |
| MIO31 | SDIO | SC SD Card socket. pin J8-8 |
| MIO32 | SDIO | SC SD Card socket. pin J8-1 |
| MIO33 | SDIO | SC SD Card socket. pin J8-2 |
| MIO36 | I²C | Ambient / Proximity Light Sensor U4, pin 2 |
| MIO37 | I²C | Ambient / Proximity Light Sensor U4, pin 1 |
| MIO39 | GPIO | Ambient / Proximity Light Sensor U4, Interrupt pin 4 |
| MIO49 | GPIO | SC SD Card socket card detect pin J8-G4 |
Table 98: Default mapping of Zynq PS MIO-bank pins
...
| Clock Source | Frequency | Clock Input Destination |
|---|---|---|
| SiTime SiT8008AI Oscillator, U8 | 33.333333 MHz | Zynq PS Bank 500, pin C7 |
Table 109: Clock sources overview
On-board LEDs
...
| LED | Color | Connected to | Signal Schematic Name | Description and Notes |
|---|---|---|---|---|
| D1 | Red | Light sensor U4, pin 6 | - | Proximity sensing functionality of light sensor U4 |
| D2 | Green | Zynq PS bank 500 | MIO7 | user configurable |
| D3 | Red | Light sensor U4, pin 9 | - | Proximity sensing functionality of light sensor U4 |
| D4 | RGB | Zynq PL bank 34, pins J15, L14, K12 | RGB_R, U1, RGB_G, U1, RGB_B, U1 | user configurable |
| D5 | Red | Light sensor U4, pin 7 | - | Proximity sensing functionality of light sensor U4 |
D6 | Green | Zynq config bank 0 | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, |
Table 1110: LEDs of the board
Connectors
...
| Board Variant | FPGA | Design | Typical Power, 25°C ambient |
|---|---|---|---|
| TE0722-02I | XC7Z010-1CLG225I | Not configured | TBD* |
| TE0722-02 | XC7Z010-1CLG225C | Not configured | TBD* |
| TE0722-02-07S-1C | XC7Z007S-1CLG225C | Not configured | TBD* |
Table 1211: Module power consumption
...
The voltages 1.0V (core voltage) and 3.3V are monitored by the voltage monitor circuit U6, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the connector pin P1-10 ('NRST') to GND. Leave this pin unconnected or connect to VDD (3.3V) when unused.
Figure 5: Voltage monitor circuit
Power Rails
Power Rail Name | J1 Pins | J2 Pins | J3 Pins | P1 Pin | P2 Pin | Direction | Notes |
|---|---|---|---|---|---|---|---|
| 3.3V | 5, 6 | 5, 6 | 5, 6 |
| 12 |
| 12 | Input |
| 3.3V power supply voltage |
Table 1312: Board power rails
Bank Voltages
Bank | Bank I/O Voltage VCCO | Voltage Range |
|---|---|---|
| 0 (config) | 3.3V | fixed |
| 500 (MIO) | 3.3V | fixed |
| 501 (MIO) | 3.3V | fixed |
| 34 (HR) | 3.3V | fixed |
| 35 (HR) | 3.3V | fixed |
Table 1413: Board bank voltages
Variants Currently in Production
| Board Variant | Xilinx Zynq SoC | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices | Zynq SoC Operating Temp. | Temp. Range |
|---|---|---|---|---|---|---|---|---|---|
| TE0722-02I | XC7Z010-1CLG225I | A9+ Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 | –40°C to +100°C | Industrial |
| TE0722-02 | XC7Z010-1CLG225C | A9+ Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 | 0°C to +85°C | Commercial |
| TE0722-02-07S-1C | XC7Z007S-1CLG225C | A9+ Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 | 0°C to +85°C | Commercial |
Table 1514: Board variants
Technical Specifications
...
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
3.3 supply voltage | -0.3 | 3.6 | V | EN5311QI datasheet / Xilinx datasheet DS187 |
| HR PL I/O banks input voltage (VCCIO single ended) | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
Storage temperature | -40 | +85 | °C | Silicon Labs Si1141/42/43 datasheet. |
Table 1615: Board absolute maximum ratings
...
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| 3.3 supply voltage | 3.3 | 3.465 | V | Xilinx datasheet DS187 |
| HR PL I/O banks input voltage (VCCIO single ended) | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS187 (VCCO 3.3V nominal) |
Operating Temperature Commercial | 0 | +85 | °C | Xilinx datasheet DS190 |
Operating Temperature Industrial | -40 | +85 | Xilinx datasheet DS190 |
Table 1716: Board recommended operating condition
...
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 02 | - | - | TE0722-02 |
| - | 01 | First production release | - | - |
Table 1817: Board hardware revision history
...
Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri, Jan Kumann |
|
Table 1918: Document change history
Disclaimer
...
Overview
Content Tools