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The 7 boot mode strapping pins (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0722 FPGA board is hardware programmed to boot initially from the on-board QSPI Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq device.

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BankTypeConnectorI/O Signal CountVoltageNotes
34HRP183.3VSignal Schematic names: 'P0' - 'P7'
34HRP283.3VSignal Schematic names: 'P24' - 'P31'
34HRP210 single ended I/O's or 5 differential pairs3.3V -
34HRJ163.3VSignal Schematic names: 'X2A' - 'X2F'
34HRJ223.3V -
34HRJ343.3VSignal Schematic names: 'X1A' - 'X1D'
35HRP18 single ended I/O's or 4 differential pairs3.3V -

Table 32: Zynq SoC PL I/O signals overview

Zynq SoC I/O Banks

BankTypeVCCIOI/O 's Signal CountAvailable on ConnectorsNotes
34HR3.3V413838 user I/O's, 3 I/O's used for controlling the RGB LED D4. 
35HR3.3V888 single ended or 4 differential.
500PS MIO3.3V70-6 MIO - pins used for QSPI flash memory interface, 1 MIO - pin connected to green LED D2.
501PS MIO3.3V100-7 MIO - pins used for SD Card interface, 3 MIO - pins connected to light sensor U4.
0Config3.3V50-4 I/O's are dedicated to JTAG interface, 'DONE'-signal is indicated by red LED D6.

Table 43: General overview of Zynq SoC PL/PS I/O banks

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JTAG Signal

J2 Connector Pin

TCK 4
TDI 9
TDO 10
TMS 8

Table 54: JTAG interface signals

Quad SPI Interface

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Zynq SoC's MIO-pinU5 PinSignal Schematic Name
MIO11SPI0-CS
MIO25SPI0-DQ0/M0
MIO32SPI0-DQ1/M1
MIO43SPI0-DQ2/M2
MIO57SPI0-DQ3/M3
MIO66SPI0-SCK

Table 65: Quad SPI interface signals and connections

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Zynq SoC's MIO-pinJ8 pinSignal Schematic Name
MIO28J8-7DAT0
MIO29J8-3CMD
MIO30J8-5CLK
MIO31J8-8DAT1
MIO32J8-1DAT2
MIO33J8-2CD/DAT3
MIO49J8-G4Card detect switch

Table 76: SD card interface signals

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Zynq SoC's MIO-pinU4 pinSignal Schematic Name
MIO362SCL
MIO371SDA

Table 87: Zynq SoC I2C interface signals

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MIO-pinFunctionConnector to
MIO1QSPIQSPI flash memory, pin 1
MIO2QSPIQSPI flash memory, pin 5
MIO3QSPIQSPI flash memory, pin 2
MIO4QSPIQSPI flash memory, pin 7
MIO5QSPIQSPI flash memory, pin 3
MIO6QSPIQSPI flash memory, pin 6
MIO7GPIOGreen LED D2
MIO28SDIOSC SD Card socket. pin J8-5
MIO29SDIOSC SD Card socket. pin J8-3
MIO30SDIOSC SD Card socket. pin J8-7
MIO31SDIOSC SD Card socket. pin J8-8
MIO32SDIOSC SD Card socket. pin J8-1
MIO33SDIOSC SD Card socket. pin J8-2
MIO36I²CAmbient / Proximity Light Sensor U4, pin 2
MIO37I²CAmbient / Proximity Light Sensor U4, pin 1
MIO39GPIOAmbient / Proximity Light Sensor U4, Interrupt pin 4
MIO49GPIOSC SD Card socket card detect pin J8-G4

Table 98: Default mapping of Zynq PS MIO-bank pins

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Clock SourceFrequencyClock Input Destination
SiTime SiT8008AI Oscillator, U833.333333 MHzZynq PS Bank 500, pin C7

Table 109: Clock sources overview

On-board LEDs

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LEDColorConnected toSignal Schematic NameDescription and Notes
D1RedLight sensor U4, pin 6- Proximity sensing functionality of light sensor U4
D2

Green

Zynq PS bank 500MIO7user configurable
D3

Red

Light sensor U4, pin 9- Proximity sensing functionality of light sensor U4
D4RGBZynq PL bank 34,
pins J15, L14, K12

RGB_R, U1,

RGB_G, U1,

RGB_B, U1

user configurable
D5RedLight sensor U4, pin 7- Proximity sensing functionality of light sensor U4

D6

Green

Zynq config bank 0

DONE

Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.

Table 1110: LEDs of the board

Connectors

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Board VariantFPGADesignTypical Power, 25°C ambient
TE0722-02IXC7Z010-1CLG225INot configuredTBD*
TE0722-02XC7Z010-1CLG225CNot configuredTBD*
TE0722-02-07S-1CXC7Z007S-1CLG225CNot configuredTBD*

Table 1211: Module power consumption

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Power Rail Name

J1 Pins

J2 PinsJ3 PinsP1 PinP2 Pin

Direction

Notes
3.3V5, 65, 65, 61212Input3.3V power supply voltage

Table 1312: Board power rails

Bank Voltages

Bank

Bank I/O Voltage VCCO

Voltage Range

0 (config)3.3Vfixed
500 (MIO)3.3Vfixed
501 (MIO)3.3Vfixed
34 (HR)3.3Vfixed
35 (HR)3.3Vfixed

Table 1413: Board bank voltages

Variants Currently in Production

 Board VariantXilinx Zynq SoC

ARM Cores

PL Cells

LUTsFlip-FlopsBlock RAM

DSP Slices

Zynq SoC Operating Temp.

Temp. Range

TE0722-02IXC7Z010-1CLG225IA9+ Dual-core28K17,6K35,2K2.1 MBytes80

–40°C to +100°C

Industrial
TE0722-02XC7Z010-1CLG225CA9+ Dual-core28K17,6K35,2K2.1 MBytes80

0°C to +85°C

Commercial
TE0722-02-07S-1CXC7Z007S-1CLG225CA9+ Single-core23K14,4K28,8K1.8 MBytes66

0°C to +85°C

Commercial

Table 1514: Board variants

Technical Specifications

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Parameter

MinMax

Units

Reference Document

3.3 supply voltage

-0.33.6

V

EN5311QI datasheet / Xilinx datasheet DS187
HR PL I/O banks input voltage (VCCIO single ended)-0.4VCCO + 0.55VXilinx datasheet DS187 (VCCO 3.3V nominal)

Storage temperature

-40

+85

°C

Silicon Labs Si1141/42/43 datasheet.

Table 1615: Board absolute maximum ratings

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ParameterMinMaxUnitsReference Document
3.3 supply voltage3.33.465 VXilinx datasheet DS187
HR PL I/O banks input voltage (VCCIO single ended)-0.20VCCO + 0.20VXilinx datasheet DS187 (VCCO 3.3V nominal)

Operating Temperature Commercial
(Variant TE0722-02 and TE0722-02-07S-1C)

0+85°CXilinx datasheet DS190

Operating Temperature Industrial
(Variant TE0722-02I)

-40+85
Xilinx datasheet DS190

Table 1716: Board recommended operating condition

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DateRevision

Notes

PCNDocumentation Link
-02 - -TE0722-02
 -

01

First production release - -

Table 1817: Board hardware revision history

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseri, Jan Kumann

  • First TRM Release

Table 1918: Document change history

Disclaimer

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