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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware


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Table of contents

Table of Contents
outlinetrue

Overview

CPLD Device with designator U1: LCMX02-256HC. Firmware with Standard Configuration for XMOD.

Feature Summary

  • JTAG routing
  • Pinheader routing

Firmware Revision and supported PCB Revision

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Product Specification

Port Description

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Name / opt. VHD NameDirectionPinDescription
Ain8XMOD Pin Header / UART RXD (input to adapter)
ACBUS4 
27FTDI / currently_not_used
ACBUS5 
28FTDI / currently_not_used
ADBUS4 
5FTDI / currently_not_used
Bout12XMOD Pin Header / UART TXD (output from adapter)
BDBUS2in21FTDI / currently_not_used
BDBUS3out20FTDI / currently_not_used
Cout9XMOD Pin Header / TCK
Din11XMOD Pin Header / TDO
Ein14XMOD Pin Header / LED
Fout13XMOD Pin Header /TDI
FT_B_RX / BDBUS1out25FTDI
FT_B_TX / BDBUS0in23FTDI
Gin17XMOD Pin Header / Pushbutton S1
Hout16XMOD Pin Header / TMS
JTAGENin26Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-1
TCK / ADBUS0in30FTDI
TDI / ADBUS1in32FTDI
TDO / ADBUS2out1FTDI
TMS / ADBUS3in29FTDI
ULEDout10LED D4 (RED)
XCLKin412 MHz OSCI Ref CLK / currently_not_used

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Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA12 pin pinheader. Access between CPLD and FPGA pinheader can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGApinheader).

UART

UART is routed through the CPLD.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV01REV03, REV02

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Work in progress

-user

No changes, also PCB REV03 compatible
2017-04-26v.7REV01REV02John HartfielREV01 finished (rework without logical changes released 2017-04-04)
2016-04-11

v.1

---REV02

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Initial release 

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