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Table of contents
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Overview
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Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Content
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For general structure and of the reference design, see see Project Delivery - Xilinx AMD devices
Design Sources
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Additional Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Design Flow
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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference DesignDesigns Overview
- Project Delivery .- AMD devices
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also TE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- Build the Debian image/Ubuntu image file with executing the "mkdebian_stretch.sh"/"mkubuntu_BionicBeaver.sh" file in Linux Terminal
- XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging AMD Development Tools#XilinxSoftwareProgrammingandDebugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Not used in this Example.
SD
- Format the SD Card with SD Card Formatter or other tool
- Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
- Copy Petalinux image.ub and Boot.bin on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section TE0820 HDMI701#Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: On TE0701 Default Firmware Boot Mode is selected via SD card (insered SD Card for SD Boot Mode) - Connect HDMI to Monitor
- Connect USB Adapter with Hub and Mouse+Keyboard
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- Debian Desktop
- Debian Desktop will be started automatically
- Use connected mouse + keyboard for interaction with GUI
- Web Browser Dillo open console and type dillo or use browser
- open console and start video or audio with "mplayer <video or audio file>"
- Ubuntu Desktop
- Ubuntu Desktop will be started automatically
- Use connected mouse + keyboard for interaction with GUI
- Web Browser Mozilla firefox can be used.
- Audio or Vider file can also be performed directly in GU
Vivado HW Manager
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System Design - Vivado
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Block Design
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PS Interfaces
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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TODO replace loc constrains with correct one for TE0820 # # TE0701 I2C Bus # set_property PACKAGE_PIN P7 [get_ports IIC_1_scl_io] set_property PACKAGE_PIN P6 [get_ports IIC_1_sda_io] set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_scl_io] set_property IOSTANDARD LVCMOS18 [get_ports IIC_1_sda_io] # # ADV7511 Interface # set_property PACKAGE_PIN L6 [get_ports hdmi_out_clk] set_property PACKAGE_PIN L7 [get_ports hdmi_out_de] set_property PACKAGE_PIN K4 [get_ports hdmi_out_hsync] set_property PACKAGE_PIN K3 [get_ports hdmi_out_vsync] set_property PACKAGE_PIN T6 [get_ports {hdmi_out_data[0]}] set_property PACKAGE_PIN R6 [get_ports {hdmi_out_data[1]}] set_property PACKAGE_PIN V9 [get_ports {hdmi_out_data[2]}] set_property PACKAGE_PIN U9 [get_ports {hdmi_out_data[3]}] set_property PACKAGE_PIN T7 [get_ports {hdmi_out_data[4]}] set_property PACKAGE_PIN N8 [get_ports {hdmi_out_data[5]}] set_property PACKAGE_PIN R7 [get_ports {hdmi_out_data[6]}] set_property PACKAGE_PIN N9 [get_ports {hdmi_out_data[7]}] set_property PACKAGE_PIN Y8 [get_ports {hdmi_out_data[8]}] set_property PACKAGE_PIN V8 [get_ports {hdmi_out_data[9]}] set_property PACKAGE_PIN W8 [get_ports {hdmi_out_data[10]}] set_property PACKAGE_PIN U8 [get_ports {hdmi_out_data[11]}] set_property IOSTANDARD LVCMOS18 [get_ports hdmi_*] set_property PACKAGE_PIN H7 [get_ports {cec_clk[0]}] set_property PACKAGE_PIN M8 [get_ports {ct_hpd[0]}] set_property PACKAGE_PIN J7 [get_ports {ls_oe[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {cec_clk[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {ct_hpd[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {ls_oe[0]}] |
Software Design - Vitis
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For SDK project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
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- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
- DMA for HDMI
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
U-Boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
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- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
CONFIG_SUBSYSTEM_ROOTFS_SD=y
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=256M"
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
U-Boot
Start with petalinux-config -c u-boot
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CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=0
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Device Tree
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/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=256M"; }; }; / { #address-cells = <2>; #size-cells = <2>; memory@0{ device-type = "memory"; reg = <0x000000000 0x00000000 0x00000000 0x80000000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hdmi_fb_reserved_region: framebuffer@7FC00000 { compatible = "removed-dma-pool"; //compatible = "shared-dma-pool"; //compatible = "xlnx,reserved-memory"; no-map; reg = <0x0 0x7FC00000 0x0 0x400000>; }; }; hdmi_fb: framebuffer@0x7FC00000 { // HDMI out compatible = "simple-framebuffer"; reg = <0x0 0x7FC00000 0x0 (1280 * 720 * 4)>; // 720p width = <1280>; // 720p height = <720>; // 720p stride = <(1280 * 4)>; // 720p format = "a8b8g8r8"; status = "okay"; }; }; &axi_vdma_0 { status = "disabled"; }; &v_tc_0 { //xilinx-vtc: probe of 43c20000.v_tc failed with error -2 status = "disabled"; }; /* SDIO */ &sdhci1 { status = "okay"; disable-wp; no-1-8-v; }; /* ETH PHY */ &gem3 { status = "okay"; ethernet_phy0: ethernet-phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <1>; }; }; /* USB 2.0 */ /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; &i2c0 { eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; |
Kernel
Start with petalinux-config -c kernel
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CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_EDAC_CORTEX_ARM64=y
- CONFIG_FB_SIMPLE
- CONFIG_LOGO
- CONFIG_LOGO_LINUX_MONO
- CONFIG_LOGO_LINUX_VGA16
- CONFIG_LOGO_LINUX_CLUT224
Rootfs
File System will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Applications
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Additional Software
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SI5338
File location <design name>/misc/Si5338/Si5338-*.slabtimeproj
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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